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IP / SOC Products News

• New PowerVR GPUs from Imagination combine advanced graphics with optimizations for vision and computational photography (Wednesday Jan. 06, 2016)
  Imagination Technologies introduces two new PowerVR Rogue GPU IP cores designed to enable customers to create advanced high definition graphics with a superior experience for vision and computational photography-based applications in their next-generation devices.
  
  
• Cadence Tensilica HiFi Audio DSP Becomes First IP Core Approved for Dolby MS12 Multistream Decoder (Wednesday Jan. 06, 2016)
  Cadence today announced that its audio core for system-on-chip (SoC) designs has been approved for using the Dolby® MS12 Multistream Decoder, an all-in-one audio solution for TVs with universal decoding, that supports Dolby Digital Plus™, Dolby®, Digita, HE-AAC decoding, Dolby Audio Processing (DAP) post-processing, system sound mixing and speaker tuning.
  
  
• Chips&Media Inc. releases its new ultra small size and low power HEVC/H.265 codec IP (Wednesday Jan. 06, 2016)
  Chips&Media Inc. a leading video codec IP provider announced today it has completed the development of ultra small size HEVC/H.265 codec IP, WAVE420L and started to license it to customers.
  
  
• PowerVR GPUs from Imagination pass OpenVX conformance with Khronos (Wednesday Jan. 06, 2016)
  Imagination Technologies announces that its PowerVR Rogue Series6 GPUs have achieved Khronos OpenVX™ 1.0.1 conformance. With OpenVX, developers can run fully optimized vision algorithms on highly parallel, power-efficient PowerVR GPUs that are used in many of the world’s leading smartphones, tablets and other products.
  
  
• Dolphin Integration unveils extremely dense audio CODECs for application processors at 28 nm and 16 nm (Monday Jan. 04, 2016)
  Dolphin Integration rolls-out its new generation of pure-logic Audio CODECs, representing the cost-effective solution for advanced processes such as 28 nm and 16 nm. Targeting a silicon area as low as 0.06 mm2 at 28 nm for the sCODi-N1-DS.01, using SESAME uHD standard cells, a new prowess has been achieved for meeting market challenges.
  
  
• CEVA Announces Certification of RivieraWaves Surf Wi-Fi 802.11ac IP Platform (Monday Jan. 04, 2016)
  CEVA, Inc. today announced that its RivieraWaves Surf IP platform has achieved Wi-Fi CERTIFIED™ ac status from the Wi-Fi Alliance®.
  
  
• Sidense Qualifies 1T-OTP Memory IP at GLOBALFOUNDRIES 55nm Low-Power Process Node (Tuesday Dec. 29, 2015)
  Sidense today announced that it has fully qualified its SiPROM one-time programmable (OTP) non-volatile memory (NVM) embedded memory products on GLOBALFOUNDRIES’ production-proven 55-nanometer (nm) Low-Power Enhanced (LPe) process technology platform.
  
  
• CEVA Releases ISO 26262 Compliant Safety Design Package for ADAS Vision Processor (Monday Dec. 28, 2015)
  CEVA, Inc. (NASDAQ: CEVA) today announced the completion of an ISO 26262 compliant safety design package that helps customers accelerate the certification of Advanced Driver Assistance Systems (ADAS) utilizing the CEVA-XM4 imaging and vision DSP.
  
  
• Mn_nH release AXI chip-to-chip interface IP and HEVC encoding expand up to 8K 30fps (Monday Dec. 28, 2015)
  Mn_nH release X2X AXI interconnection IP for chip to chip communication. X2X AXI chip to chip interface IP enable equivalent AXI functionality and performance but less I/O usage with raising the rate of utilisation of AXI signal. And X2X IP provide system to system, cpu to cpu and bus to bus freely accessible functions between chip and another chip.
  
  
• Xylon Expands Its Portfolio of Computer Vision IP Cores for Advanced Driver Assistance (ADAS) with the Driver Drowsiness Detector (Tuesday Dec. 22, 2015)
  The new logiDROWSINE Driver Drowsiness Detector IP core detects driver drowsiness and distraction based on facial movements monitored through a camera placed in a vehicle cabin. The
  
  
• Intellitech Granted US Patent for Pay-per-Instance IP core Licensing (Monday Dec. 21, 2015)
  Intellitech® Corporation, the technology leader in solutions for IEEE 1149.1-2013 Silicon Instrument development, has announced it has been granted US patent 9,152,749 entitled "Management system, method and apparatus for licensed delivery and accounting of electronic circuits".
  
  
• Arasan announces the Industry's First MIPI DSI V1.3 Controller IP Cores (Thursday Dec. 17, 2015)
  Arasan Chip Systems announces support for MIPI DSI v1.3 with support for Display Stream Compression, Sub links, Deskew, and Checksum for Test Mode.
  
  
• Think Silicon Launches NEMA|PICO The World Smallest, Most Ultra-Low Power and Cost Efficient 2D GPU at CES 2016 (Tuesday Dec. 15, 2015)
  Think Silicon announced today the release and immediate availability of NEMA|p(PICO) the world smallest (0.07mm2 die-area, two times smaller than the competition) and most power efficient (0.05 mW leakage) 2D Graphics Processor Unit (GPU).
  
  
• Dolphin Integration helps reducing BoM cost of IoT circuits thanks to a Panoply of Over Voltage regulators (Monday Dec. 14, 2015)
  For SoCs supplied by Lithium-Ion or Alkaline batteries, the actual voltage ranges from 4.4 V in their life, down to 2.0 V over time. They empower IoT devices, which are most of the time put in sleep mode in order to extend their battery life, requiring ultra low voltage supplies for their Always-on and retention domains.
  
  
• Cortus Launches Low-Power Floating Point Processor for Intelligent Connected Devices (Thursday Dec. 10, 2015)
  Cortus, a technology leader in low power, silicon efficient, 32-bit processor IP, announced the release of the FPS26 single precision floating point IP core today, the third in a family of products based on the Cortus v2 instruction set. The core is aimed at embedded systems requiring good floating point computational performance while also delivering small silicon area and low power dissipation.
  
  
• SMIC and M31 Introduce Differentiated IP Solutions for Various Storage Controller Applications (Thursday Dec. 10, 2015)
  SMIC and M31 Technology jointly announced today that SMIC will expand its IP portfolio with M31's differentiated high speed interface IP solutions.
  
  
• Sidense Qualifies 1T-OTP Memory IP at SMIC 130nm and 110nm Processes (Thursday Dec. 03, 2015)
  Sidense Corp., a leading developer of non-volatile memory OTP IP cores, today announced that it has fully qualified its SiPROM one-time programmable (OTP) non-volatile memory (NVM) embedded memory products at SMIC's (Semiconductor Manufacturing International Corporation) 130nm and 110nm G processes.
  
  
• Kandou Delivers One Terabit Per Second of Chip-to-Chip Bandwidth at Less Than One Watt (Thursday Dec. 03, 2015)
  Kandou Bus announced today that their Glasswing physical interface SerDes block, code named GW28-125-USR, has been fully tested and demonstrates the capability to achieve one terabit per second of chip-to- chip link bandwidth at less than one watt of power consumed. The chip was designed and built by Kandou’s engineering teams from Switzerland, the UK, and the US and was fabricated in TSMC’s 28nm HPM process.
  
  
• Credo Delivers Industry's Lowest Power 16nmFF+ 28G LR-Compliant SerDes IP With Comprehensive Development Platform (Wednesday Dec. 02, 2015)
  Credo Semiconductor today announced the commercial availability of a complete development platform for its advanced 28G SerDes IP on the TSMC 16nmFF+ process node.
  
  
• Seamless Devices Introduces New Analog Signal Processing Solutions That Aim to Enhance the Effectiveness of LTE, WiFi and Microwave Applications (Tuesday Dec. 01, 2015)
  Seamless Devices, Inc. is pleased to introduce a set of analog front-end (AFE) solutions that aim to make it easier for architects of signal processing systems to address the tradeoff between performance quality and power usage in electronic devices.
  
  
• Pleora Expands Market-Proven GigE Vision IP Core with Xilinx FPGA Support (Monday Nov. 30, 2015)
  Pleora Technologies today increased design flexibility for imaging device manufacturers by expanding its market-proven GigE Vision® IP core platform to include support for field programmable gate arrays (FPGAs) from both Xilinx and Altera.
  
  
• Ultra-low power 32-bit microcontroller with advanced power modes from Dolphin Integration (Monday Nov. 30, 2015)
  In order to meet the long battery-life requirements in the growing market of IoT devices, energy saving becomes a paramount concern, specifically the reduction of static power consumption when devices spend up to 99.9 % of the time in an inactive mode.
  
  
• RFEL announces the Correlator AX for real time, multiple Unique Pattern detection across thousands of data streams (Monday Nov. 30, 2015)
  RFEL has announced its new multi-channel, multi-rate correlator IP (Intellectual Property). The high performance Correlator AX™ core offers high sensitivity Unique Pattern (UP) detection from multiple, interleaved data streams with differing sample rates.
  
  
• Altera Functional Safety Package Combines FPGA Flexibility with "Lockstep" Processor Solution to Reduce Risk and Time-to-Market (Monday Nov. 23, 2015)
  Altera today announced the availability of the Altera® Functional Safety Lockstep solution for the Nios® II embedded processor, a solution that reduces risk in design cycles and helps system designers simplify certification for industrial and automotive safety applications.
  
  
• CEVA Introduces New Low Power Communication DSPs to Address the Multimode Connectivity Requirements of IoT and M2M (Wednesday Nov. 18, 2015)
  CEVA, Inc. (NASDAQ: CEVA), the leading licensor of DSP and IP platforms for cellular, multimedia and connectivity, today introduced two new power- and cost-optimized communication processors designed specifically to address the growing demand for multimode connectivity solutions for the Internet of Things (IoT) and Machine-to-Machine (M2M) applications.
  
  
• Sonics Upgrades SoC Development Environment And Flagship NoC To Improve Chip Architecture Optimization And SoC Resiliency (Tuesday Nov. 17, 2015)
  Sonics today introduced new versions of its SonicsStudio® system-on-chip (SoC) development environment and SonicsGN® NoC.
  
  
• IPextreme Joins Forces With NXP to Bring Silicon Proven USB Technology to Market (Tuesday Nov. 17, 2015)
  IPextreme today announced a partnership to bring NXP Semiconductors’ family of silicon-proven USB IP cores to market.
  
  
• Arasan Announces The Industry's First MIPI SLIMBus v2.0 IP Core (Monday Nov. 16, 2015)
  Arasan Chip Systems, Inc. (“Arasan”), a leading provider of Total IP Solutions for SoC providers, announces availability of IP compliant with MIPI SLIMbus® standard v 2.0 released by the MIPI association on November 4, 2015.
  
  
• Barco Silex launches lightning-fast IP core for public-key cryptography to secure Internet-of-Things (Monday Nov. 16, 2015)
  Barco Silex has launched a new IP core for public-key cryptography. The new core boosts the performance of Barco Silex’s best-in-class solutions reaching less than 150 µs to perform an ECDSA-P256 verify operation, even on FPGA.
  
  
• Minimizing BoM cost and silicon area thanks to Dolphin Integration's iLR-LaDiable capless regulator (Monday Nov. 16, 2015)
  IoT and wearable devices have added to the challenge of reduction of BoM cost and silicon area that of changing the principles of voltage regulators to the point that their efficiency is no longer the major criteria.