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IP / SOC Products News

• Synopsys Launches High-Performance Embedded Vision Processor IP (Monday Mar. 30, 2015)
  Synopsys today announced the availability of the first products in the new DesignWare® EV Family of vision processors. The EV52 and EV54 vision processors are fully programmable and configurable vision processor IP cores that combine the flexibility of software solutions with the low cost and low power consumption of dedicated hardware.
  
  
• Semtech Announces IP Collaboration with MorethanIP to Support Ethernet at Speeds of 25G, 50G, 100G and 400G (Monday Mar. 30, 2015)
  MorethanIP Completes Interoperability Testing using Semtech’s PHY Connected to their Ethernet 10/25/40/50/100 Gigabit PCS (Physical Coding Sub-Layer) IP with Reed Solomon FEC (RS-FEC) and Fire Code FEC (FC-FEC) Support
  
  
• World's Fastest 8051 IP Core from Digital Core Design is 29 times faster (Monday Mar. 30, 2015)
  Digital Core Design introduced the DQ8051 IP Core. DCD’s new extremely-fast 8051 MCU Core boasts a Dhrystone 2.1 performance rating of 0.27292 DMIPS/MHz, which therefore enables a 29.01 times speed-up over the original 80C51 chip operating at the same frequency.
  
  
• Andes and eMemory Announce New IC Security Solutions For IoT Security Applications (Monday Mar. 30, 2015)
  Targeting the market demands, eMemory Technology, the logic non-volatile memory (Logic NVM) and silicon intellectual property (Silicon IP) industry leader, partnered with Andes Technology Corporation, the first developer of original 32-bit microprocessor IP and system IC design in Asia, to launch new IC security solutions for IoT security applications market.
  
  
• Mobiveil's Smallest Footprint Low-Density Parity Check LDPC-Based Flash Reliability IP Provides Extended Durability for NVM Express-Based Solid-State Drives (Friday Mar. 27, 2015)
  Mobiveil today announced Low-Density Parity Check LDPC-based flash reliability IP that offers solid-state drive (SSD) System on Chip (SoC) and FPGA designers a silicon footprint half the size of other LDPC IP blocks currently on the market.
  
  
• Faraday Announces Its Silicon-proven MIPI Subsystem to Enable Faster Time-to-Market (Thursday Mar. 26, 2015)
  Faraday Technology today announced the availability of its MIPI subsystem of Camera Serial Interface (CSI-2) and Low-Voltage Differential Signaling (LVDS) in UMC’s 40nm LP process.
  
  
• Sidense Increases its Coverage of the Popular 28nm Node (Thursday Mar. 26, 2015)
  Sidense today announced that the Company’s SHF 1T-OTP macros for GLOBALFOUNDRIES 28nm HPP and SLP processes have met all of GLOBALFOUNDRIES qualification requirements.
  
  
• Digital Blocks Announces 2nd Gen Audio/Video & Data Hardware Protocol Stacks Supporting MPEG2 Transport Stream (TS), RTP, and UDP/IP Protocols (Tuesday Mar. 24, 2015)
  Digital today announces 2nd Generation Hardware Protocol Stacks supporting a mix of MPEG2 Transport Stream (TS), RTP, and UDP/IP Protocols for network adapter cards with 10/100/1000 Mbps or 10/40/100 Gbps network links.
  
  
• Xilinx Announces Availability of 100G RS-FEC IP for Data Center, Service Provider, and Enterprise Applications (Wednesday Mar. 18, 2015)
  Xilinx, Inc. today announced availability of its 100G IEEE 802.3bj Reed-Solomon FEC (RS-FEC) IP for data center, service provider, and enterprise applications. The 100G RS-FEC IP enables new emerging optical solutions such as SR4, CWDM4, PSM4 or ER4f.
  
  
• SHA 256-bit hash generator by Noesis Technologies (Monday Mar. 16, 2015)
  
  
  
• Synopsys and Hardent Provide Interoperable Display IP Solutions to Reduce Data Transmission Bandwidth for Ultra High-Definition Mobile Devices (Thursday Mar. 12, 2015)
  Synopsys and Hardent today announced availability of a compliant and interoperable Display Serial Interface (DSI) solution that helps reduce the data transmission bandwidth in Ultra-High Definition (UHD) mobile devices.
  
  
• Integre Technologies Announces Low Cost, High Performance x1 HyperLink DSP Interface FPGA Core (Thursday Mar. 12, 2015)
  Integre Technologies today announced the release of the single lane IP-HyperLink high speed digital signal processor (DSP) interface core for both Altera and Xilinx device families.
  
  
• UMC Broadens its 55nm eFlash Platform with Faraday's Silicon-proven IP (Thursday Mar. 12, 2015)
  Faraday and UMC today announced the availability of a complete set of low power consumption fundamental IPs developed for UMC’s 55nm Low Power (LP) embedded Flash process.
  
  
• Alma Technologies Announces Availability of a New Ultra High Throughput JPEG Encoder IP Core (Monday Mar. 09, 2015)
  Alma Technologies today announced the immediate availability of a new very high performance JPEG Encoder IP Core, initiating a new product line of scalable parallel processing Ultra High Throughput Image and Video Compression IPs.
  
  
• Dolphin Integration innovates for detection practices on voice activity with WhisperTrigger (Monday Mar. 09, 2015)
  While voice activity detection is considered as a must-have for a growing range of applications such as wearable devices or smart home appliances, Dolphin Integration innovates with the stand-alone WhisperTrigger™. Whereas the voice detection function is usually handled by a DSP or a voice processor, it now becomes possible to leave the rest of the SoC in stand-by or sleep mode while leaving only the WhisperTrigger™ in always-on mode.
  
  
• SilabTech announces the release of its JESD204B Compliant 12.5Gbps SERDES PHY and Controller (Thursday Mar. 05, 2015)
  SilabTech, leading supplier of High Speed Interface intellectual property designs (IPs), announced today the release of its JESD204B SERDES PHY and Controller. SilabTech has already delivered this JESD204B SERDES and Controller to its early licensees including a top tier semiconductor company. These products SERDES has been validated in the TSMC 28nm HPM process, while the controller is a soft IP designed to support a wide range of process technology nodes.
  
  
• Digital Core Design introduces DI2CM targeting I2C design needs (Wednesday Mar. 04, 2015)
  Digital Core Design introduced soft IP Core, targeting I2C design needs. The DI2CM core provides an interface between a microprocessor or microcontroller and the I2C bus. It can work as a master transmitter or master receiver - depending on a working mode, determined by the microcontroller.
  
  
• Vivante Announces Support for Vulkan GPU Rendering and Compute Standards (Tuesday Mar. 03, 2015)
  Vivante­ welcomes today's Khronos Group's announcement at GDC of the new Vulkan open standard API—an innovative, ground-up design that will unleash the newest innovations inside Vivante's latest GPU hardware.
  
  
• Mellanox and Synopsys Demonstrate Industry's First PCIe 4.0 Interoperability (Tuesday Mar. 03, 2015)
  Mellanox today announced that it has collaborated with Synopsys to bring the industry’s first demonstration of interoperability between Synopsys’ DesignWare® PHY IP for PCI Express® (PCIe®) 4.0 and Mellanox’s PCIe 4.0 port to the PCI-SIG® Developers Conference Israel.
  
  
• Imagination packs high-quality PowerVR Rogue graphics into a tiny footprint (Monday Mar. 02, 2015)
  Imagination Technologies announces a new area-optimized PowerVR GPU designed to drive high-quality graphics with full OpenGL ES 3.0 functionality into low-cost and space-constrained devices.
  
  
• New PowerVR video IP family from Imagination combines highest quality H.265/H.264 encoding with optimized low latency streaming (Monday Mar. 02, 2015)
  
  
  
• VeriSilicon Introduces Hantro G2v2 Multi-format Decoder IP with VP9 Profile 2 to Support 10-bit Premium Internet Content (Monday Mar. 02, 2015)
  VeriSilicon announces today the availability of Hantro G2v2 Multi-format Decoder IP to support Google’s VP9 Profile 2. This profile was introduced by the WebM project in 2014 to meet the industry’s requirement for higher precision content.
  
  
• PLDA and Analog Bits Partner to Provide a Silicon-proven PCIe 3.0 Solution for leading 28nm low power process (Monday Mar. 02, 2015)
  PLDA has added Analog Bits, the semiconductor industry’s leading provider of mixed-signal IP, to its ecosystem of PHY partners. Together, the partners have developed a silicon-proven PCIe Gen 3 solution for a leading 28nm low-power process node that offers ASIC engineers great power savings and improved performance.
  
  
• Shikino Launches Still Image Decoder IP Obtaining "World-class speed" 16X faster image processing (Monday Mar. 02, 2015)
  Shikino developed this still image decoder IP which has the world’s first image processing performance, 16X speed (16 data/clock), in the JPEG decompression with high bit depths (8-bit/10-bit/12-bit). The product is most suitable for the mobile/broadcasting/ medical/aerospace fields and so forth.
  
  
• Altera and Escape Communications Announce High-capacity Turn-key Modem Solution for E- and V-band Microwave Radios (Friday Feb. 27, 2015)
  Altera and Escape Communications today announced the availability of a high-performance, cost-effective and scalable microwave modem solution that that enables rapid system development and accelerates production shipments for microwave backhaul and fronthaul applications.
  
  
• Cadence Achieves First PCI Express 2.0 and PCI Express 3.0 Compliance for TSMC 16nm FinFET Plus Process (Wednesday Feb. 25, 2015)
  Cadence today announced that its multi-protocol Serializer/Deserializer (SerDes) PHY IP for PCI Express® (PCIe®) 2.0 and PCIe 3.0 technology for TSMC’s 16nm FinFET Plus (16FF+) process have passed PCI-SIG® compliance testing.
  
  
• Blu Wireless to demonstrate HYDRA gigabit modem IP targeted at mmWave communication (Wednesday Feb. 25, 2015)
  Blu Wireless announces the successful validation of the lead implementation in 40nm CMOS of its HYDRA IP. Blu Wireless’s HYDRA gigabit modem is aimed at millimetre wave communication applications including ‘WiGig’ 802.11ad and wireless Back Haul for LTE mobile networks.
  
  
• CEVA Brings Human-Like Intelligent Vision Processing to Low-Power Embedded Systems (Wednesday Feb. 25, 2015)
  CEVA today unveiled the CEVA-XM4, its fourth-generation imaging and vision processor IP. Building on the success of the CEVA-MM3101, the CEVA-XM4 is equipped with specific functionality required to solve the most critical challenges faced when implementing energy-efficient human-like vision and visual perception capabilities in embedded systems.
  
  
• Tronics Expands its Business Model to Mobile and Wearable Applications with the Licensing of its Combo Sensors Based on Disruptive Magelan and M&NEMS Technologies (Wednesday Feb. 25, 2015)
  Tronics has stepped up its strategic deployment by providing the industry with the most advanced solutions for mobile and wearable applications. This key milestone enables the Company to offer state of the art products and technologies to new players in high volume markets.
  
  
• Xilinx and Xylon Announce New Industry Leading Automated Multi-Camera Image Stitching IP for 2D/3D Surround View Systems (Tuesday Feb. 24, 2015)
  Xilinx and Xylon today announced new industry leading automated multi-camera image stitching IP for 2D/3D surround view systems. The Automotive logiADAK 3.0 Advanced Driver Assistance Development Kit with logiOWL IP enables on-target, full vehicle level multi-camera calibration in seconds for Tier One automotive electronics suppliers and OEM automakers.