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IP / SOC Products News

• Dolphin Integration enable Dongbu HiTek's users to benefit from their ultra high density standard cell library (Monday May. 26, 2014)
  Dolphin Integration and Dongbu HiTek technical partnership enables their users to benefit of their ultra high density standard cell library called SESAME at 130 nm CIS.
  
  
• Synopsys Unveils Industry's First Complete PCI Express 4.0 IP Solution (Thursday May. 22, 2014)
  Synopsys today introduced the industry's first complete PCI Express 4.0 IP solution, consisting of DesignWare PHY, controllers and verification IP (VIP) targeting enterprise computing applications such as servers, networking, storage systems and solid state drives (SSDs).
  
  
• OmniPhy Announces 2.5v I/O Transistor based Mixed Signal PHY Availability in TSMC 28nm HPM (Thursday May. 22, 2014)
  OmniPhy announced the availability of its Interface PHY product line on Taiwan Semiconductor Manufacturing (TSMC) 28nm HPM process, designed using 2.5v I/O transistors.
  
  
• GUC Unveils Its First 16nm IP (Thursday May. 22, 2014)
  Global Unichip Corp. (GUC) revealed today that it has successfully silicon proved 16nm DDR4 IP at TSMC, making it one of GUC’s first IP available for TSMC’s 16nm FinFET (16FF) process. The new 16FF DDR4 PHY IP operates at up to 3.2 gigabytes per second (Gbps), a 50 percent increase in speed over previous generation DDR3 IP, while reducing power by 25 percent at the same speed.
  
  
• Uniquify Announces UniquiPHY DDR System Analyzer (Wednesday May. 21, 2014)
  Uniquify today announced the release of the UniquiPHY™ DDR System Analyzer (DSA), a comprehensive software package that provides designers with a suite of automated DDR analysis, visualization and debug tools.
  
  
• Uniquify Announces Immediate Availability of LPDDR4 Memory Subsystem IP (Tuesday May. 20, 2014)
  Uniquify today announced immediate availability of its LPDDR4 memory IP, including the memory controller IP and PHY models, for low-power, high-performance applications, including mobile and handheld products.
  
  
• IP Cores, Inc. Ships an FPGA Version of Its 100 Gbps MACsec Statistics IP Core (Tuesday May. 20, 2014)
  IP Cores has announced shipments of an FPGA version of the MACsec statistics add-on core for its popular MSP10 MACsec encryption/decryption core for line-speed MACsec processing targeting the 100 Gbps Ethernet solutions.
  
  
• Cadence Offers Immediate Availability of DDR4 PHY IP on TSMC 16nm FinFET Process (Tuesday May. 20, 2014)
  Cadence Design Systems today announced immediate availability of DDR4 PHY IP (intellectual property) built on TSMC’s 16nm FinFET process.
  
  
• Sonics Introduces Next-Generation Development Environment To Ease Semiconductor IP Integration For Heterogeneous Multicore SoCs (Monday May. 19, 2014)
  Sonics today introduced its next-generation SonicsStudio development environment that addresses the integration challenges of complex system-on-chip (SoC) designs that include multiple processor and intellectual property (IP) cores
  
  
• Cadence Announces Availability of IP Solutions on 28nm FD-SOI Process (Thursday May. 15, 2014)
  Cadence today announced the immediate availability of two IP solutions for third-party designs on the 28nm FD-SOI process node that is accessible via the recently announced agreement between STMicroelectronics and Samsung Electronics.
  
  
• Uniquify Delivers High-Performance DDR3 Memory System Running in Low-Cost, Wire Bond Package (Thursday May. 15, 2014)
  Uniquify today announced that it has achieved an ultrafast DDR3 performance of 2100 megabits per second (Mbps) in a low-cost wire bond package. The DDR3 IP subsystem is implemented in a customer design in a low-power 28-nanometer (nm) process for a high-volume consumer application that requires the use of a low-cost wire bond package.
  
  
• Arasan Chip Systems Announces the Industry's First SD 4.1 and eMMC 5.0 Combined Host Controller (Tuesday May. 13, 2014)
  Arasan announced today the availability of the industry’s first combined SD 4.1, SDIO 4.1, eMMC 5.0 Host Controller. Arasan’s long-standing active contributor status to both SDA and JEDEC allows a first to market advantage with both storage card and embedded Flash memory controllers for mobile applications.
  
  
• Kilopass' Gusto Ultra-Low Power NVM IP for Code Storage Enabled on UMC 55nm LP Process (Tuesday May. 13, 2014)
  Kilopass and UMC today announced the availability of Kilopass’ Gusto low power NVM IP on UMC’s 55nm LP process following successful completion of 1000 hours of JEDEC standard reliability testing.
  
  
• 12-bit Extended JPEG Decoder Further Extends Compression Options Available from CAST (Thursday May. 08, 2014)
  A new decoder IP core for the 12-bit Extended JPEG image format is now available from semiconductor intellectual property provider CAST, Inc. One of the few such cores available, the JPEG-D-X 12-bit Decoder Core is sourced from Alma Technologies and is intended for applications requiring images with a greater dynamic range—such as medical imaging and machine vision—or to provide significantly better graphic quality with easy system integration and modest resource use—as in advanced automotive control and display systems
  
  
• Uniquify Demonstrates Fastest DDR4 Memory Performance in Silicon for TSMC's 28HPM Process Technology (Thursday May. 08, 2014)
  Uniquify announced today it has achieved the industry’s fastest DDR4 performance in silicon of 2800 megabits per second (Mbps). The combination of Uniquify’s adaptive DDR4 intellectual property (IP) and SK Hynix’s high-performance DDR4 SDRAM memory components is operating at 2800Mbps in a system implemented using TSMC’s 28HPM process technology.
  
  
• IP Cores, Inc. Announces NIST SP800-90B Update for Its True Random IP Cores (Tuesday May. 06, 2014)
  IP Cores, Inc. announces compact version of its true random IP cores compliant with the new revisions of the NIST SP800-90Arev1, SP800-90B, SP800-90C.
  
  
• DCD's I2C IP Core requires no programming (Monday May. 05, 2014)
  DCD’s DI2CSB IP Core is a two wire, bidirectional serial bus, which provides stable and efficient short distance data transmission between numerous devices. A very simple interface, composed with read, write and data signals, allows easy connection to target device. The DI2CSB is a technology independent design, that’s why it can be implemented in a variety of both ASIC and FPGA technologies.
  
  
• Sidense 1T-OTP NVM Qualified in Second-Generation TSMC 180nm BCD Process (Wednesday Apr. 30, 2014)
  Sidense today announced that the Company's 1T-OTP macros for TSMC's 180nm BCD 1.8/5.0V Gen 2 process have met all TSMC9000 Assessment program requirements.
  
  
• CEVA Unveils Bluetooth Solution for CEVA-TeakLite-4 DSP Targeting Low Power, Always-on, Smart Connected Devices (Wednesday Apr. 30, 2014)
  CEVA today announced that the CEVA-TeakLite-4 DSP is now handling the processing load of Bluetooth, in addition to audio, voice and sensing technologies, thereby dramatically lowering the cost, complexity and power consumption of chip designs targeting smartphones, the Internet of Things (IoT), wearables and wireless audio devices.
  
  
• Synopsys' New Silicon-Proven DesignWare USB 3.0 and USB 2.0 femtoPHY IP Cut Area by 50 Percent (Tuesday Apr. 29, 2014)
  Synopsys today announced that it has reduced the area of USB PHY implementations by up to 50 percent with the new DesignWare® USB femtoPHY IP, minimizing USB PHY silicon footprint and cost for designs in 28-nanometer (nm) and 14/16-nm FinFET processes.
  
  
• Sonics Extends Flagship On-Chip Network Product, Addresses Low Latency SoC Designs for the Wearable Market (Tuesday Apr. 29, 2014)
  Sonics today introduced the latest version of SonicsGN™, which provides greater configurability to meet the performance requirements of systems-on-chip (SoC) being designed for wearable devices as well as wireless handheld, wired consumer, and communications infrastructure devices.
  
  
• DINI Group Verifies Compatibility of Northwest Logic's PCI Express Cores with Virtex-7 ASIC Prototyping Platforms (Tuesday Apr. 29, 2014)
  Northwest Logic and DINI Group announced today that Northwest Logic’s PCI Express® (PCIe®) 3.0 solution, including the Expresso 3.0 Core (PCI Express 3.0 Controller Core) has been validated on DINI Group’s 1, 2, and 4-FPGA ASIC prototyping platforms. This validation was done with 4 lanes running at 5 Gbit/s SERDES rates.
  
  
• Alchip and Credo Provide 28Gbps SerDes ASICs for Enterprise Data Communication (Wednesday Apr. 23, 2014)
  Credo Semiconductor, a global innovation leader in SerDes technology, and Alchip Technologies, Ltd. (TWSE: 3661), a world leading fabless ASIC company, announced a strategic partnership for providing 28Gb/s SerDes IP for ASIC solutions targeting the Data Center and Enterprise Communications markets.
  
  
• Synopsys Announces Industry's First Complete LPDDR4 IP Solution for High-Performance, Low-Power Mobile SoC Designs (Wednesday Apr. 23, 2014)
  Synopsys today introduced the industry's first complete LPDDR4 IP solution, which includes Synopsys' DesignWare® LPDDR4 multiPHY, Enhanced Universal DDR Memory Controller (uMCTL2) and verification IP (VIP), as well as hardening and signal integrity services
  
  
• Krivi announces 28nm silicon proven DDR3/3L PHY with ARM CoreLink Technology (Wednesday Apr. 23, 2014)
  Krivi Semiconductor has announced its initial working silicon of a 28nm DDR3 PHY. The new Krivi DDR3/3L PHY with ARM® CoreLink™ DMC-400 Dynamic Memory Controller is JEDEC compatible, feature rich and supports maximum speeds of up to 2.133Gbps. Synthesizable and PnR friendly, this latest RTL from Krivi supports custom floor-planning to suit modern SoC providers who require faster-time-to-market or more stringent overall PHY area requirements.
  
  
• Dolphin Integration announce the availability of the TSMC sponsored sROMet and DpRAM generators at 90 nm LP eFlash (Wednesday Apr. 23, 2014)
  The high-density and low-power foundry-sponsored generators, sROMet PHOENIX and DpRAM ERIS (HVT and SVT), are now available in the eFlash process variant for the 90 nm node.
  
  
• Athena Announces Fastest Elliptic Curve Cryptography Accelerator Core (Monday Apr. 21, 2014)
  The Athena Group, Inc., the leader in high-performance public key (PK) and elliptic curve cryptography (ECC), today announced the industry’s fastest ECC accelerator core. Athena’s commitment to maintaining leadership in the high-performance PK cryptography and ECC marketplace is reinforced with the release of the EC Ultra family of dedicated ECC accelerators. Athena introduced three variants ranging in performance from 2,000 to 8,000 NIST P-256 EC-DSA verify operations per second.
  
  
• Memoir Systems Introduces Renaissance Memory Uptime for Next Generation SoCs (Monday Apr. 21, 2014)
  Memoir Systems Inc., today introduced Renaissance Memory Uptime IP, a solution that protects against the growing threat of catastrophic memory failure due to multi-bit errors. The high performance SOCs at the heart of data center equipment are highly integrated and often have hundreds of megabits of embedded memory.
  
  
• Xilinx and Open-Silicon Announce Hybrid Memory Cube Controller IP for All Programmable FPGAs (Monday Apr. 21, 2014)
  Xilinx and Open-Silicon, Inc., both founding developer members of the Hybrid Memory Cube Consortium (HMCC), today announced Hybrid Memory Cube (HMC) controller IP for Xilinx Virtex®-7 FPGAs
  
  
• Credo Semiconductor Breaks Through the 50Gb/s NRZ Serial Data Rate Barrier - Deliver The Most Advanced SerDes (Thursday Apr. 17, 2014)
  Credo Semiconductor today announced the industry's first SerDes transceiver that can deliver speeds up to 55Gb/s NRZ signaling. The SerDes (Serializer-Deserializer) was developed for the next generation 40G/100G/400G data center and enterprise networking applications.