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I3C Host Controller v1.2

• Compliant with MIPI I3C Specification v1.2
• Compliant with MIPI I3C HCI Specification v1.1
• Supports up to 12.5 MHz operation using Push-Pull

AV1/HEVC/AVC/VP9 Video Decoder HW IP 8K30fps@500MHz

• High-quality encoding
• Improved bandwidth efficiency
• Low delay encoding

MIPI C-PHY v2.0 D-PHY v2.1 RX for TSMC N6

• Compliant with the MIPI D-PHY specification, v2.1
• 4 Lanes in D-PHY mode up to 6.5Gb/s per lane
• Compliant with the MIPI C-PHY specification, v2.0

Safety Enhanced General Purpose Neural Processing Unit (NPU)

• Hybrid Von Neuman + 2D SIMD matrix architecture
• 64b Instruction word, single instruction issue per clock
• 7-stage, in-order pipeline

Logic based Hardware Root-of-Trust - Physical Unclonable Function (PUF)

• Secure provisioning
• Secured identities
• High entropy seeds

On-Die PDN Analyzer for Transistor-Level Visibility and Telemetry

• Transistor-level PDN visibility
• PDN telemetry and onboard analytics across the silicon lifecycle

10G Base T Ethernet PHY

• CAD Proven database
• Ready to go for fabrication and characterization
• ASIC volume production ( in future)

LPDDR5X/5/4X PHY IP on TSMC N3P

• Low latency, small area, low power
• Compatible with JEDEC standard LPDDR5X, LPDDR5 and LPDDR4X SDRAMs up to 8533 Mbps

Audio Sample Rate Converter

• Studio-Grade Audio Quality
• Scalable and Efficient
• Fast Synchronization

Lightweight Root-of-Trust

• Rapidly implement secure boot and attestation capabilities without significant area, cost, or complexity overhead.
• Prevent malicious software attacks, unauthorized access, and firmware tampering to safeguard critical device functionality.

2kx8 Bits OTP (One-Time Programmable) IP, TSM- 40ULP 1.1/2.5V Process

• Small IP size
• Low program voltage/current
• Low read voltage/current

Dual Port Register File Compiler (1 Read-Only Port, 1 Write-Only Port)

• Ultra Low Standby Current
• .72V to .88V
• Internal Bist Mux

RapidIO 2.0 PHY & Controller

TSMC FPD-Link / OpenLDI / LVDS forwarded clock SERDES Link

• Universal LVDS-based interfaces supporting variety of Tx and Rx configurations.

TSMC 55nm 12-Bit 8-Input 1M/200k SAR ADC

UCIe and BOW Universal PHY

• Novel Redundancy for Hi-Rel,
• Support for 16&18-bit wide data,
• Support Synchronous Operation,

PCIe refclk buffer (14nm)

PCIe 5.0 Serdes PHY IP, Silicon Proven in TSMC 12FFC

UniPHY™ IoT IP: Ultra Low Power and Smallest PHY area for low cost Chiplets

• 0.25mm2 compared to 1.5mm2
• Low-cost technology support
• No PLL required

MIPI C-PHY v1.1

• Compliant to MIPI Alliance Standard for C-PHY specification Version 1.0
• Supports standard PHY transceiver compliant to MIPI Specification

CCSDS (8160,7136) LDPC Encoder

SPI FLASH Controller with Execute in place – XIP (SINGLE, DUAL and QUAD SPI Bus Controller with DDR / DTR support and optional AES Encryption)

PCIe2.0 PHY & Controller

MIPI C-PHY/D-PHY Combo DSI RX (Receiver) IP in TSMC 22ULP

• Dual mode PHY Supports MIPI Alliance Specification D-PHY v2.5 & C-PHY v2.0
• Consists of 1 Clock lane and 4 Data lanes in D-PHY mode