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MIPI D-PHY Tx-Only 2 Lanes in TSMC (28nm, 22nm, 16nm, 12nm, N7, N6)
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40-450MHz Programmable Clock Generator PLL, SMIC0.13um
The AR530S13 is a low power programmable phase locked loop (PLL) featured with wide output frequency range from 50MHz to 450MHz. The PLL synchronizes two output clocks with an external reference clock through the locked loop mechanism. The output duty cycle is adjusted to 50%, independent to the reference clock. The PLL contains built-in 6-bit reference divider, 12-bit feedback divider and two 4-bit output divider that may be used in combination to provide flexible output frequencies.
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