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I3C Host Controller v1.2

• Compliant with MIPI I3C Specification v1.2
• Compliant with MIPI I3C HCI Specification v1.1
• Supports up to 12.5 MHz operation using Push-Pull

AV1/HEVC/AVC/VP9 Video Decoder HW IP 8K30fps@500MHz

• High-quality encoding
• Improved bandwidth efficiency
• Low delay encoding

MIPI C-PHY v2.0 D-PHY v2.1 RX for TSMC N6

• Compliant with the MIPI D-PHY specification, v2.1
• 4 Lanes in D-PHY mode up to 6.5Gb/s per lane
• Compliant with the MIPI C-PHY specification, v2.0

Safety Enhanced General Purpose Neural Processing Unit (NPU)

• Hybrid Von Neuman + 2D SIMD matrix architecture
• 64b Instruction word, single instruction issue per clock
• 7-stage, in-order pipeline

Logic based Hardware Root-of-Trust - Physical Unclonable Function (PUF)

• Secure provisioning
• Secured identities
• High entropy seeds

On-Die PDN Analyzer for Transistor-Level Visibility and Telemetry

• Transistor-level PDN visibility
• PDN telemetry and onboard analytics across the silicon lifecycle

10G Base T Ethernet PHY

• CAD Proven database
• Ready to go for fabrication and characterization
• ASIC volume production ( in future)

LPDDR5X/5/4X PHY IP on TSMC N3P

• Low latency, small area, low power
• Compatible with JEDEC standard LPDDR5X, LPDDR5 and LPDDR4X SDRAMs up to 8533 Mbps

Audio Sample Rate Converter

• Studio-Grade Audio Quality
• Scalable and Efficient
• Fast Synchronization

Lightweight Root-of-Trust

• Rapidly implement secure boot and attestation capabilities without significant area, cost, or complexity overhead.
• Prevent malicious software attacks, unauthorized access, and firmware tampering to safeguard critical device functionality.

2kx8 Bits OTP (One-Time Programmable) IP, TSM- 40ULP 1.1/2.5V Process

• Small IP size
• Low program voltage/current
• Low read voltage/current

Dual Port Register File Compiler (1 Read-Only Port, 1 Write-Only Port)

• Ultra Low Standby Current
• .72V to .88V
• Internal Bist Mux

AV1/HEVC/AVC/VP9 Video Decoder HW IP 8K30fps@500MHz

• High-quality encoding
• Improved bandwidth efficiency
• Low delay encoding

ONFI 4.2 PHY

HBM4 Memory Controller

• Supports HBM4 memory devices
• Supports all standard HBM4 channel densities (up to 32 Gb)
• Supports up to 10 Gbps/pin

HDMI1.4 TX PHY

UCIe-S PHY for Standard Package (x16) for Automotive in TSMC (N5A)

UCIe based 8-bit 48-Gsps Transceiver (ADC/DAC/PLL/UCIe)

• 48-Gsps peak sample rate
• 8 bit resolution
• UCIe SP (16x lanes at 16Gbps) with streaming controller

UCIe based 12-bit 12-Gsps Transceiver (ADC/DAC/PLL/UCIe)

• 12-Gsps peak sample rate
• 12 bit resolution (programmable)
• UCIe SP (16x lanes at 16Gbps) with streaming controller

Aeonic Generate™ AWM3

• Droop and DFS/DVFS response profile
• Programmable droop and DFS/DVFS response rate

Perceptual Video Quality Optimization IP

• Fully hardwired IP
• High performance
• Codec-agnostic

ISP, Image Signal Processing, Real-time Pixel Processor for Automotive

• Very low latency
• no frame-buffer

HDMI 2.1/DisplayPort 2.1 TX PHY in TSMC (N3E, N3P)

INNOLINK-B PHY