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I3C Host Controller v1.2

• Compliant with MIPI I3C Specification v1.2
• Compliant with MIPI I3C HCI Specification v1.1
• Supports up to 12.5 MHz operation using Push-Pull

AV1/HEVC/AVC/VP9 Video Decoder HW IP 8K30fps@500MHz

• High-quality encoding
• Improved bandwidth efficiency
• Low delay encoding

MIPI C-PHY v2.0 D-PHY v2.1 RX for TSMC N6

• Compliant with the MIPI D-PHY specification, v2.1
• 4 Lanes in D-PHY mode up to 6.5Gb/s per lane
• Compliant with the MIPI C-PHY specification, v2.0

Safety Enhanced General Purpose Neural Processing Unit (NPU)

• Hybrid Von Neuman + 2D SIMD matrix architecture
• 64b Instruction word, single instruction issue per clock
• 7-stage, in-order pipeline

Logic based Hardware Root-of-Trust - Physical Unclonable Function (PUF)

• Secure provisioning
• Secured identities
• High entropy seeds

On-Die PDN Analyzer for Transistor-Level Visibility and Telemetry

• Transistor-level PDN visibility
• PDN telemetry and onboard analytics across the silicon lifecycle

10G Base T Ethernet PHY

• CAD Proven database
• Ready to go for fabrication and characterization
• ASIC volume production ( in future)

LPDDR5X/5/4X PHY IP on TSMC N3P

• Low latency, small area, low power
• Compatible with JEDEC standard LPDDR5X, LPDDR5 and LPDDR4X SDRAMs up to 8533 Mbps

Audio Sample Rate Converter

• Studio-Grade Audio Quality
• Scalable and Efficient
• Fast Synchronization

Lightweight Root-of-Trust

• Rapidly implement secure boot and attestation capabilities without significant area, cost, or complexity overhead.
• Prevent malicious software attacks, unauthorized access, and firmware tampering to safeguard critical device functionality.

2kx8 Bits OTP (One-Time Programmable) IP, TSM- 40ULP 1.1/2.5V Process

• Small IP size
• Low program voltage/current
• Low read voltage/current

Dual Port Register File Compiler (1 Read-Only Port, 1 Write-Only Port)

• Ultra Low Standby Current
• .72V to .88V
• Internal Bist Mux

ONFI 4.2 PHY

AES GCM IP Core

• supports encryption and decryption for modes listed below:
• supports offline and online key schedule
• supports 128, 192 and 256-bit key lengths
• has masked and non-masked modes

Die-to-Die, 112G Ultra-Extra Short Reach PHY in TSMC (12nm, N7, N6, N5)

DDR5/4 PHY in GF (12nm)

LPDDR5X/5/4X/4 combo PHY at 12nm

TSMC 3nm (N3E) 1.2V LVDS Tx/Rx with 1.8V BGR

TSMC 6nm (6FF) 3.3V GPIO

LPDDR5X/5/4X/4 PHY IP for 12nm

HBM3 PHY IP at 7nm

• Unbeatable performance-driven and low-power-driven PPA
• Ultra-low read/write latency with programmable PHY boundary timing

DualPHY 100/1000BASE-T1 22FDX

• GlobalFoundries, 22FDX
• Combo-PHY IP

Bluetooth low energy v5.4 Baseband Controller, Protocol Software Stack and Profiles IP

High Performance Fractional-N RF Frequency Synthesizer PLL in UMC 40LP

• Fractional-N digital PLL architecture, using an LC-tank oscillator
• Ultra-low jitter and ultra-low phase noise