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I3C Host Controller v1.2

• Compliant with MIPI I3C Specification v1.2
• Compliant with MIPI I3C HCI Specification v1.1
• Supports up to 12.5 MHz operation using Push-Pull

AV1/HEVC/AVC/VP9 Video Decoder HW IP 8K30fps@500MHz

• High-quality encoding
• Improved bandwidth efficiency
• Low delay encoding

MIPI C-PHY v2.0 D-PHY v2.1 RX for TSMC N6

• Compliant with the MIPI D-PHY specification, v2.1
• 4 Lanes in D-PHY mode up to 6.5Gb/s per lane
• Compliant with the MIPI C-PHY specification, v2.0

Safety Enhanced General Purpose Neural Processing Unit (NPU)

• Hybrid Von Neuman + 2D SIMD matrix architecture
• 64b Instruction word, single instruction issue per clock
• 7-stage, in-order pipeline

Logic based Hardware Root-of-Trust - Physical Unclonable Function (PUF)

• Secure provisioning
• Secured identities
• High entropy seeds

On-Die PDN Analyzer for Transistor-Level Visibility and Telemetry

• Transistor-level PDN visibility
• PDN telemetry and onboard analytics across the silicon lifecycle

10G Base T Ethernet PHY

• CAD Proven database
• Ready to go for fabrication and characterization
• ASIC volume production ( in future)

LPDDR5X/5/4X PHY IP on TSMC N3P

• Low latency, small area, low power
• Compatible with JEDEC standard LPDDR5X, LPDDR5 and LPDDR4X SDRAMs up to 8533 Mbps

Audio Sample Rate Converter

• Studio-Grade Audio Quality
• Scalable and Efficient
• Fast Synchronization

Lightweight Root-of-Trust

• Rapidly implement secure boot and attestation capabilities without significant area, cost, or complexity overhead.
• Prevent malicious software attacks, unauthorized access, and firmware tampering to safeguard critical device functionality.

2kx8 Bits OTP (One-Time Programmable) IP, TSM- 40ULP 1.1/2.5V Process

• Small IP size
• Low program voltage/current
• Low read voltage/current

Dual Port Register File Compiler (1 Read-Only Port, 1 Write-Only Port)

• Ultra Low Standby Current
• .72V to .88V
• Internal Bist Mux

112G LR-Max Ethernet PHY for TSMC N5

• Supports 1.25 to 112 Gbps data-rate
• Supports PCI Express 6.0, 1G to 400G/800G Ethernet, CCIX, CXL, JESD204C, CPRI, SATA, and OIF CEI LR/MR/VSR Electrical Interfaces protocols

TSMC 55nm 12-Bit 8-Input 1M/200k SAR ADC

112Gb/s PAM4 SERDES PHY (14nm)

112G Ethernet PHY for TSMC N5

• Supports 1.25 to 112 Gbps data-rate
• Supports PCI Express 6.0, 1G to 400G/800G Ethernet, CCIX, CXL, JESD204C, CPRI, SATA, and OIF CEI LR/MR/VSR Electrical Interfaces protocols

10Base-T/100Base-TX Fast Ethernet PHY

• Comply with IEEE 802.3u and IEEE 802.3 standard
• Support IEEE 802.3az 2010 Energy Efficient Ethernet

PCIe Gen 6 SerDes IP

• PCie Gen 5/6 compliant
• Up to 112G PAM 4 support
• less than 6 pj/bit typical power consumption

LPDDR4x/5 Secondary/Slave (memory side!) PHY

• Supports JEDEC standard LPDDR5, LPDDR4X, LPDDR4
• Secondary side PHY
• Custom implementations available

TSMC CLN7FF 7nm Clock Generator PLL

• 800MHz-4000MHz
• Delivers optimal jitter performance over all multiplication settings.

USB2.0 PHY & Controller

2-16Gbps Multi-Protocol IO Supporting BOW, OHBI and UCIe

• Efficiency
• Composability
• Programmability

Ethernet 10/100 PHY

LVDS IO in SMIC 28HKC+, upto 1.6Gbps

• Brite LVDS IO libraries can support data rate up to 2000Mbps with 2.5V and 1.8V power, based on 28nm HK and 40nm LL process.