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1t-otp memory IP Listing

3639 IP Cores (1 - 40)

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Inline Memory Encryption (IME) Security Module for DDR/LPDDR

As our connected world expands, the technological advances in high-performance computing (HPC) are reshaping system-on-chip (SoC) designs to address the need for more acceleration, more storage ...

1
DDR4 Memory Controller

Rambus DDR4 Controller Core from Rambus is designed for use in applications requiring high memory throughput, high clock rates and full programmability. The core accepts commands using a ...

2
DDR3 Memory Controller

Rambus’s DDR3 Controller Core offered by Rambus is designed for use in applications requiring high memory throughput, high clock rates and full programmability. The core accepts commands ...

3
HBM3E/3 Memory Controller

The Rambus HBM3E/3 Controller Cores are designed for use in applications requiring high memory throughput, low latency and full programmability. The cores accept commands using a simple ...

1 Testimonial
June Paik, CEO, Furiosa

4
GDDR7 Memory Controller

The Rambus GDDR7 controller core is designed for use in applications requiring high memory throughput including graphics, high performance computing (HPC), and artificial intelligence/machine ...

5
HBM4 Memory Controller

The Rambus HBM4 Controller Core is designed for use in applications requiring high memory bandwidth and low latency including AI/ML, HPC, advanced data center workloads and graphics. The ...

6
The SST SuperFlash® IP is an embedded CMOS Flash memory IP with sector/chip Erase and byte Program capability.

SuperFlash® is SST’s patented and proprietary NOR flash technology. With 80B+ devices shipped, SuperFlash is the non-volatile memory of choice for embedded applications. In high-volume production ...

7
HBM2/2E Memory Controller Core

The Rambus HBM2/2E Controller Core is designed for use in applications requiring high memory throughput, low latency and full programmability. The core accepts commands using a simple local ...

3 Testimonials
Arthur Zhang, COO, Enflame Technology

8
GDDR6 Memory Controller

Rambus GDDR6 Controller Core is designed for use in applications requiring high memory throughput, high clock rates and full programmability. The core accepts commands using a simple local ...

1 Testimonial
Serge Leef, Microsystems Technology Office Program Manager, DARPA

9
DDR4/3, LPDDR5x/5/4x/4 Memory Controller IP

OPENEDGES, the memory system IP provider, including DDR memory controller, DDR PHY, on-chip interconnect, and NPU IP together as an integrated solution or independent IP. They are tightly combined ...

10
High Performance DDR5/4/3 Memory Controller

Mobiveil's DDR5/4/3 Memory Controller is a highly flexible and configurable design targeted for high performance enterprise server and real-time consumer applications that utilize computational ...

11
Hyperbus Flash Memory Controller

Emerging high-performance applications demand increasingly fast read throughputs from NOR-flash memory devices. At the same time, the pin-count required to implement the memory subsystem should ...

12
Ultra High-Speed Cache Memory Compiler

Silvaco’s Ultra High-Speed cache memory is an adaptable, independent, non-coherent cache Intellectual Property (IP) featuring an advanced cache architecture. This architecture enhances ...

13
Magillem Registers System Integration Automation

Cost-effective and scalable, Magillem Registers offers a unified methodology for HW/SW Interface automation. The Registers approach targets the traditional need to manage registers efficiently ...

14
LPDDR4x/5 Secondary/Slave (memory side!) PHY

This LPDDR4/4X/5 PHY is a memory-side interface IP normally found implemented within commodity DRAM products. Green Mountain Semiconductor's LPDDR4X/LPDDR5 combo IP provides the unique opportunity ...

15
LPDDR4x Secondary/Slave (memory side!) PHY

This LPDDR4X PHY is a memory-side interface IP normally found implemented within commodity DRAM products. Green Mountain Semiconductor's LPDDR4X IP provides the unique opportunity to transmit ...

16
LPDDR5 Secondary/Slave (memory side!) PHY

This LPDDR5 PHY is a memory-side interface IP normally found implemented within commodity DRAM products. Green Mountain Semiconductor's LPDDR5 IP provides the unique opportunity to transmit ...

17
LPDDR5X Secondary/Slave (memory side!) PHY

This LPDDR5X PHY is a memory-side interface IP normally found implemented within commodity DRAM products. Green Mountain Semiconductor's LPDDR5X IP provides the unique opportunity to transmit ...

18
LPDDR5X/5/4X/4 Memory Controller IP

OPENEDGES, the memory system IP provider, including DDR memory controller, DDR PHY, on-chip interconnect, and NPU IP together as an integrated solution or independent IP. They are tightly combined ...

19
Secure-IC's Securyzr™ Memory & Bus Protection IP Core

The Memory & Bus Protection IP Core module enables on-the-fly encryption/decryption and authentication to the external memory. It supports AHB/AXI slave/master interfaces, APB port ...

20
xSPI Flash Memory Controller

The xSPI-MC core is a versatile serial flash memory controller, which allows a system to easily detect and access the attached flash device or directly boot from it. The controller core supports ...

21
LPDDR4/3, DDR4/3 Memory Controller IP

OPENEDGES, the memory system IP provider, including DDR memory controller, DDR PHY, on-chip interconnect, and NPU IP together as an integrated solution or independent IP. They are tightly combined ...

22
GDDR6 Memory Controller IP

OPENEDGES, the memory system IP provider, including DDR memory controller, DDR PHY, on-chip interconnect, and NPU IP together as an integrated solution or independent IP. They are tightly combined ...

23
High Performance HBM, HBM3 Memory Controller

OPENEDGES, the memory system IP provider, including DDR memory controller, DDR PHY, on-chip interconnect, and NPU IP together as an integrated solution or independent IP. They are tightly combined ...

24
CXL memory expansion

DenseMem increases effective CXL Type 3 Device memory capacity by a factor of 2x through transparent, in-line memory compression/decompression with minimal impact to latency and badwidth. DenseMem ...

25
AHB-Lite General Purpose Memory Module

The Roa Logic AHB-Lite Memory IP is a fully parameterized soft IP implementing on-chip memory for access by an AHB-Lite based Master. All signals defined in the AMBA 3 AHB-Lite v1.0 specifications ...

Try this IP for Free!

26
High Bandwidth Memory 3 (HBM3/3E) IP optimized for Samsung SF4X

SkyeChip’s HBM3 IP consists of a PHY and memory controller optimized for Samsung SF4X process to support the HBM3 memory standard (JESD238A) operating at up to 9.6 Gbps/pin. The HBM3 IP is ...

27
65nm OTP Non Volatile Memory for Standard CMOS Logic Process

NSCore's PermSRAM(R) is the only embedded CMOS, one time programmable (OTP), non-volatile RAM IP of its kind, utilizing the 'hot carrier effect' to trap charge in the sidewall spacer of the ...

28
65nm FTP Non Volatile Memory for Standard CMOS Logic Process

NSCore's PermSRAM(R) is the only embedded CMOS, one time programmable (OTP), non-volatile RAM IP of its kind, utilizing the 'hot carrier effect' to trap charge in the sidewall spacer of the ...

29
180nm OTP Non Volatile Memory for Standard CMOS Logic Process

NSCore's PermSRAM(R) is the only embedded CMOS, one time programmable (OTP), non-volatile RAM IP of its kind, utilizing the 'hot carrier effect' to trap charge in the sidewall spacer of the ...

30
180nm FTP Non Volatile Memory for Standard CMOS Logic Process

NSCore's PermSRAM(R) is the only embedded CMOS, one time programmable (OTP), non-volatile RAM IP of its kind, utilizing the 'hot carrier effect' to trap charge in the sidewall spacer of the ...

31
90nm OTP Non Volatile Memory for Standard CMOS Logic Process

NSCore's PermSRAM(R) is the only embedded CMOS, one time programmable (OTP), non-volatile RAM IP of its kind, utilizing the 'hot carrier effect' to trap charge in the sidewall spacer of the ...

32
90nm FTP Non Volatile Memory for Standard CMOS Logic Process

NSCore's PermSRAM(R) is the only embedded CMOS, one time programmable (OTP), non-volatile RAM IP of its kind, utilizing the 'hot carrier effect' to trap charge in the sidewall spacer of the ...

33
130nm OTP Non Volatile Memory for Standard CMOS Logic Process

NSCore's PermSRAM(R) is the only embedded CMOS, one time programmable (OTP), non-volatile RAM IP of its kind, utilizing the 'hot carrier effect' to trap charge in the sidewall spacer of the ...

34
130nm FTP Non Volatile Memory for Standard CMOS Logic Process

NSCore's PermSRAM(R) is the only embedded CMOS, one time programmable (OTP), non-volatile RAM IP of its kind, utilizing the 'hot carrier effect' to trap charge in the sidewall spacer of the ...

35
180nm MTP Non Volatile Memory for Standard CMOS Logic Process

NSCore's TwinBit(TM) is the only embedded CMOS, multi-time programmable (MTP), non-volatile RAM IP of its kind, utilizing the 'hot carrier effect' to trap charge in the sidewall spacer of the ...

36
FTP Non Volatile Memory for Standard TSMC 40nm ULP Process

TwinBit(TM)FTP is the only embedded CMOS, few-time programmable (FTP), non-volatile RAM IP of its kind, utilizing the 'hot carrier effect' to trap charge in the sidewall spacer of the gate. ...

37
MTP Non Volatile Memory for TSMC 180nm BCD Process

NSCore's TwinBit(TM) is the only embedded CMOS, multi-time programmable (MTP), non-volatile RAM IP of its kind, utilizing the 'hot carrier effect' to trap charge in the sidewall spacer of the ...

38
55nmHV MTP Non Volatile Memory for Standard CMOS Logic Process

NSCore's TwinBit(TM) is the only embedded CMOS, multi-time programmable (MTP), non-volatile RAM IP of its kind, utilizing the 'hot carrier effect' to trap charge in the sidewall spacer of the ...

39
DMA AXI4-Stream to/from AXI4 Memory Map - Scatter-Gather Descriptor List

The Digital Blocks DB-DMAC-MC2-DL-MM2S-S2MM Verilog RTL IP Core is a Multi-Channel Scatter-Gather DMA Controller that transfers data between AXI4 Memory Map and AXI4-Stream Interfaces. Control ...

40

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