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Jtag IP Listing

307 IP Cores (1 - 40)

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Dolphin JTAG Controller (TAP)

Dolphin Technology provides JTAG Controller (TAP) IP which enables access through the JTAG interface for building designs with efficient, fast, and productive debugging solutions. The IP's size ...

1
Dolphin JTAG Controller

Dolphin Technology provides JTAG Controller (TAP) IP which enables access through the JTAG interface for building designs with efficient, fast, and productive debugging solutions. The IP's size ...

2
JTAG 2-Wire to 4-Wire Adapter

The OT4001_cjtag is an adapter which permits legacy IEEE 1149.1 ports to communicate as an IEEE 1149.7 2-wire OScan1 cJTAG port. A simple update to a 1149.1 port to support 1149.7 2-wire signaling. ...

3
IEEE1149.1-2001 JTAG access port

The Beyond TAP Controller is a fully IEEE 1149.1-2001 compatible JTAG Test Access Port (TAP) Controller. It is used for development and debugging purposes like Boundary Scan, Memory BIST. The ...

4
JTAG & ACJTAG IP

Most modern systems use high-speed, AC-coupled deferential pairs. While 1149.1 is an excellent tool for testing and diagnosing digital systems, it was designed for DC-coupled, TTL-level nets. ...

5
JTAG to AXI Master

The LogiCORE™ JTAG to AXI Master IP core is a customizable core that can generate the AXI transactions and drive the AXI signals internal to FPGA in the system. This supports AXI4 interfaces ...

6
Device Secure Debug

The Joint Test Action Group (JTAG) is the IEEE1149.1 Standard Test Access Port (TAP) and Boundary Scan Architecture. Giving a full access to the internal system components of the device, the ...

7
(SDR) Software Defined Radio for high end 4G/ 5G and large MIMO application

This SDR is a development platform for realization networks like 4G/5G and other radio applications involving more than 4 or 8 antenna ports. The SDR platforms have the mix of practical deployment ...

8
cjTAG IEEE 1149.7 Compact TAP Controller

The IEEE 1149.7 Compact TAP from Silvaco provides an IEEE 1149.7-compliant Test Access Port (TAP), enabling you to take advantage of IEEE 1149.7 features such as: - 2-pin access to your on-chip ...

9
cjTAG IEEE 1149.7 DTS Adapter

The DTS Adapter from Silvaco enables an existing IEEE 1149.1 debug test system (DTS) to take advantage of the advanced debug/test capabilities available with today’s IEEE 1149.7-enabled semiconductor ...

10
IEEE 1149.7 Compact TAP IP

IEEE 1149.7 COMPACT TAP is full-featured, easy-to-use, synthesizable design, compatible with IEEE 1149.7 Compliant. Through its IEEE 1149.7 COMPACT TAP compatibility,it provides a simple interface ...

11
IEEE 1149.7 DTS Adapter IP

IEEE 1149.7 DTS Adapter is full-featured, easy-to-use, synthesizable design, compatible with IEEE 1149.7 Compliant. Through its IEEE 1149.7 DTS ADAPTER compatibility,it provides a simple interface ...

12
High-Performance, Configurable, 8-bit Microcontroller Core

This 8051 IP core implements a range of fast, 8-bit, 8051-compatible microcontrollers that execute the MCS®51 instruction set. The R8051XC2 IP core runs with a single clock per machine cycle, ...

1 Testimonial
Matt Jones, VP of Strategic Marketing, Rambus

13
On-Chip Logic Analyzer

The LOGAN - On-chip Logic Analyzer IP core can trace and display on-chip signals. When armed, the on-chip logic analyzers stores the traced signals in the circular buffer until a trigger condition ...

14
Parameterizable RAM Built In Self Test

Fully static, synthesizable RAM BIST ; Independent Set of Test Algorithms for Application specific Test Coverage ; RAM Structure independent Algorithms ; Data Retention Rest ; Single Port ...

15
Parameterizable ROM Built In Self Test Controller

Fully static, synthesizable ROM BIST ; ROM Structure independent CRC Algorithms ; Master Slave, simultaneous multiple ROM Test ; Optional transparent Bypass Mode (hidden ROM test during scan ...

16
Ultra low power, high-performance DSP / controller RISC core

Based on its long standing expertise in ultra low power processors for the Swiss watch industry, CSEM now offers three architectures in its icyflex family of ultra low-power processors: icyflex2 ...

17
Synthesizable 68000 Compatible CPU Core

The V68000 is a synthesizable VHDL (soft) core design which is object code compatible with Motorola's popular MC68000. The V68000 is intended to be used in system-on-a-chip applications constructed ...

18
Synthesizable 6800 Compatible CPU Core

The V6800 is a synthesizable VHDL (soft) core design which is object code compatible with Motorola's popular 8-bit MC6800 microprocessor. The V6800 is intended to be used in system-on-a-chip ...

19
High Performance 8051 Compatible CPU Core

The V805x is a synthesizable VHDL (soft) core design which is object code compatible with Intel's popular 8-bit 8051 microprocessor. The V805x is intended to be used in system-on-a-chip applications ...

20
ARM7TDMI-S compatible Microcontroller Core

Binary Compatible to standard ARM7TDMITM ; Patent free ; Single Clock, fully Static Design ; 32 Bit RISC Architecture ; JTAG Test Port ; AMBA Bus Master ; AMBA AHB Bus Interface ; 200 MHz Clock ...

21
High Performance Media Processor

PACT offers XPP-III cores as synthesizable Verilog RTL Code. XPP-III is built from only a few different components which are linked with pipelined point-to point connections. This allows to ...

22
Quad 1.06/1.25/2.125/1.56/2.5/3.125 Gbps Backplane SerDes

TRC3104SBA is a Quad SerDes transceiver device, capable of transmitting 1.06 to 3.125Gb/s signals over Backplane, Fiber Channel, and cupper cables. It uses single and double data rate capability. ...

23
10Gbps XAUI Transceiver

TRC3114 is a Quad SerDes used as four independent 3.125Gb/s FC, BP, or cable transceiver or 10Gbps XAUI Transceive. It operates with a single 1.8V supply. It has built-in 8bit/10bit converter, ...

24
MicroBlaze Debug Module (MDM)

The datasheet provides the design specification for the MicroBlaze Debug Module (MDM). The MDM core enables JTAG-based debugging of one or more MicroBlaze processors.

25
ARM9 compatible Microcontroller Core (ARM9xxT, ARM9xxE)

Binary Compatible to standard ARM9TDMI ; Patent free ; Single Clock, fully Static Design ; 32 Bit RISC Architecture ; JTAG Test Port ; AMBA Bus Master ; AMBA AHB Bus Interface ; 200 MHz Clock ...

26
High-Performance Low-Power 32-bit RISC core

The C310 is a member of theC*Core TM High-Performance Low-Power 32-bit RISC core family. It has been designed for high-performance and cost-sensitive embedded applications, with particular emphasis ...

27
CoreMP7

Microsemi's CoreMP7 is a soft IP version of the popular ARM7TDMI-S™ that has been optimized to maximize speed and minimize size in Microsemi's Flash-based FPGAs. CoreMP7 ...

28
Serial GMII 1.25 Gbps Phy

SGMII IP Phy is Serial Giga bit Media Independent Interface (SGMII) IP core and provides a single lane 1.25Gbps date rate interface to MAC layer and consists of Physical Convergent Sublayer ...

29
16 bit DSP fixed point coprocessor

The APS DSP is a 16 bit fixed point RISC signal processing co-processor designed to extend the APS family of processors from Cortus. It fully exploits the co-processor interface, ensuring the ...

30
ARM 32-bit FPGA Optimized Processor

Developed by ARM in collaboration with Actel, the 32-bit ARM Cortex-M1 processor is the first ARM processor designed for FPGA implementation. With a balance between size and speed, the free ...

31
GPON OLT BMCDR SerDes

Downstream speed: 2.488Gbps/1.244Gbps data rate ; Upstream speed: 1.244Gbps/622Mbps/155Mbps data rate ; ITU GPON ONU/OLT compliant (G.984.2) ; High-speed differential reference clock ; Jitter ...

32
1.06/2.125/4.25 Gbps Fibre Channel and Backplane SerDes

Quad SerDes optimized for Fibre Channel and backplane applications ; Supports data rates from 1.0625/2.125 and 4.25 Gbps speeds ; High-speed differential reference clock ; Low jitter clock synthesizers ...

33
LVDS Transmitter 1250Mb/s, 800Mhz clock with RSDS support

V-Trans 's LVDS technology solutions eliminate the trade-offs in speed, low power, low noise (EMI), and BOM cost saving for high performance data transmission applications. This LVDS transmitter ...

34
LVDS Receiver 1250Mb/s, 800Mhz clock

V-Trans 's LVDS technology solutions eliminate the trade-offs in speed, low power, low noise (EMI), and BOM cost saving for high performance data transmission applications. This LVDS receiver ...

35
ChipScope Integrated Controller (ICON)

The LogiCORE® IP ChipScope Pro Integrated core (ICON) provides an interface between the JTAG Boundary Scan (BSCAN) interface of the FPGA device and the ChipScope Pro cores, including the following ...

36
Xilinx MicroBlaze Trace Core (XMTC)

This document provides the design specification for the Xilinx MicroBlaze Trace Core (XMTC), which provides instruction and data trace capabilities for MicroBlaze™ processors.

37
ChipScope Pro IBERT for Spartan-6 GTP Transceivers

The LogiCORE™ ChipScope™ Pro Integrated Bit Error Ratio Tester (IBERT) core for the Spartan®-6 GTP transceiver is a customizable core that can be used to evaluate and monitor the health ...

38
ChipScope Pro IBERT for Virtex-6 FPGA GTX Transceivers

The LogiCORE™ ChipScope™ Pro Integrated Bit Error Ratio Tester (IBERT) core for Virtex®-6 FPGA GTX transceivers can be used to evaluate and monitor GTX transceivers. The design includes ...

39
ChipScope Pro IBERT for Virtex-5 FPGA GTX Transceivers

The ChipScope™ Pro Integrated Bit Error Ratio Tester (IBERT) core for Virtex®-5 FPGA GTX transceivers is a customizable core that can be used to evaluate and monitor the health of the GTX ...

40

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