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Pcie gen2 ip cores IP Listing

110 IP Cores (1 - 40)

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PCIe 5.0 Serdes PHY IP, Silicon Proven in TSMC 12FFC

This Peripheral Component Interconnect Express (PCIe) x4 PHY is compliant with PCIe 5.0 Base Specification with support of PIPE 5.1 interface spec. Lower power consumption is achieved due to ...

1
PCIe 5.0 PHY

With sophisticated architecture and advanced technology, KNiulink SerDes PHY IP with PMA and PCS layer is designed for low power and high performance application. PCS layer and PMA layer include ...

2
Low Power PCIe2/SATA3SERDES PHY - TSMC 28HPC

Analog Bits Programmable SERDES provides a Physical Media Attachment (PMA) Layer capable of signaling at multiple data rates and supports multi-protocol market needs including a wide range of ...

3
PCIe3 SSCG PLL - GLOBALFOUNDRIES 12LP+

Analog Bits’ PCIe Gen3 SSCG PLL addresses stringent performance requirements in high-speed serial link applications that support the PCI Express Gen3 serial bus standard where SRIS (Separate ...

4
PCIe Gen2 PHY

* Endpoint or Root Complex * PIPE includes skip insertion, deletion * PCIe power savings modes * Port bifurcation support

5
PCIe 4.0 PHY

With sophisticated architecture and advanced technology, KNiulink SerDes PHY IP with PMA and PCS layer is designed for low power and high performance application. PCS layer and PMA layer include ...

6
USB 3.0/ PCIe 2.0/ SATA 3.0 Combo PHY IP, Silicon Proven in TSMC 22ULP

The PHY combo comprises Serial ATA (SATA) compliant with SATA 3.0 Specification, Peripheral Component Interconnect Express (PCIe) compliant with PCIe 2.0 Base Specification supporting PIPE interface ...

7
PCIe 3.0/2.0 PHY

With sophisticated architecture and advanced technology, KNiulink PCIE GEN3/GEN2 PHY IP with PMA and PCS layer is designed for low power and high performance application. It is fully compatible ...

8
MIPHY Consumer SerDes IP, Silicon Proven in ST 28FDSOI

Consumer Multimedia Applications: Wide support of Consumer PHY standards such as PCIe Gen1/2/3, USB 3.0 Super Speed, JESD204B, SATA Gen 1/2/3 and SGMII / QSGMII from 1.125 Gb/s to 8Gb/s / 10 ...

9
PCIe Controller IP, PCIe Gen-2 with the AHB interface, x1 Lanes, Soft IP

PCI Express Gen 2 Endpoint Controller. Support single-function, virtual channel and single lane.

10
PCIe Controller IP, PCIe Gen-2 with the AXI interface, x4 Lanes, Soft IP

PCIe Gen2 x4 Lane Endpoint Controller.

11
PCI Express Gen2 PHY IP, PCIe Gen-2, 1 Lanes, UMC 55nm SP process

PCIE Gen.II, UMC 55nm SP/RVT Low-K Logic process.

12
PCI Express Gen2 PHY IP, PCIe Gen-2, 1 Lanes, UMC 90nm SP process

PCI-Express II PHY, UMC 90nm SP/RVT Low-K process.

13
PCI Express Gen2 PHY IP, PCIe Gen-2, 4 Lanes, UMC 90nm SP process

4x lane PCI Express Gen II PHY, UMC 90nm SP/RVT Low-K Logic process.

14
PCIE Gen6 digital controller (End Point)

PCIE is a layered protocol high speed interconnect interface supporting speeds up to 64GT/S and multi lanes and links. The layers specified in PCIE specification Transport, Datalink, Physical ...

15
PCIE Gen6 digital controller (Root Complex)

PCIE is a layered protocol high speed interconnect interface supporting speeds up to 64GT/S and multi lanes and links. The layers specified in PCIE specification Transport, Datalink, Physical ...

16
PCIE Gen6 digital controller (Dual Mode)

PCIE is a layered protocol high speed interconnect interface supporting speeds up to 64GT/S and multi lanes and links. The layers specified in PCIE specification Transport, Datalink, Physical ...

17
PCIe DMA Controller (Low Latency)

The RapidDMA IP solution offers a fully integrated, highly-configurable, multi-channel and low latency PCIe-DMA solution. The IP solution is optimized for high performance and low latency and ...

18
7 Series Gen2 Integrated Block for PCI Express (PCIe)

Xilinx provides a 7 Series FPGA solution for PCI Express® (PCIe) to configure the 7 Series FPGA Integrated Block for PCIe and includes additional logic to create a complete solution for PCIe. ...

19
AXI Memory Mapped to PCI Express (PCIe) Gen2

The AXI Memory Mapped to PCIe® Gen2 IP core provides an interface between the AXI4 interface and the Gen2 PCI Express (PCIe) silicon hard core. The AXI4 PCIe provides full bridge functionality ...

20
PCIe Gen2 PHY

The PCIe2 PHY is a complete mixed-signal semiconductor intellectual property (IP) solution, designed for single-chip integration into PCI Express applications. The PCIe 2 PHY pcie2_pipe_PxL_xN ...

21
PCIe Gen4 RX/TX IP (2-Lane) supporting 16, 8, 5, 2.5Gb/s interface.

The Teletrx_8999 is a high-performance two-lane PCI-Express Gen4 IP. It follows PCIe Gen4 spec, supporting data rate up to 16Gb/s. It supports both common clock and independent reference clock ...

22
PCIe 5.0 Controller supporting Endpoint, Root Port, Switch, Bridge and advanced features

Rambus PCIe 5.0 Controller is a configurable and scalable PCIe controller Soft IP designed for ASIC and FPGA implementation. Rambus PCIe 5.0 Controller is compliant with the PCI Express 5.0 ...

2 Testimonials
June Paik, CEO, Furiosa

23
PCIe 5.0 Controller with AMBA AXI interface

Rambus PCIe 5.0 Controller is a configurable and scalable PCIe controller Soft IP designed for ASIC and FPGA implementation. Rambus PCIe 5.0 Controller is compliant with the PCI Express 5.0 ...

1 Testimonial
Russel Lindsay, Sr. Product Manager, Anritsu Corporation

24
PCIe 5.0 Customizable Embedded Multi-port Switch

Rambus PCIe 5.0 Multi-port Switch is a customizable, Embedded PCIe Switch designed for ASIC and FPGA implementations enabling the connection of one upstream port and multiple downstream ports ...

25
PCIe 4.0 Controller supporting Endpoint, Root Port, Switch, Bridge and advanced features

Rambus PCIe 4.0 Controller is a configurable and scalable PCIe controller Soft IP designed for ASIC and FPGA implementation. The Rambus PCIe 4.0 Controller is compliant with the PCI Express ...

26
PCIe 4.0 Controller with AMBA AXI interface

Rambus PCIe 4.0 Controller is a configurable and scalable PCIe controller Soft IP designed for ASIC and FPGA implementation. The Rambus PCIe 4.0 Controller is compliant with the PCI Express ...

27
PCIe Gen3 to SRIO Gen3 Bridge (FPGA)

Mobiveil’s PCIe Gen3 to SRIO Gen3 Bridge is a high-performance FPGA-based protocol conversion IP that enables seamless communication between PCI Express (PCIe) and Serial RapidIO (SRIO) systems. ...

28
Multi-Link Multi-Protocol SerDes 16Gbps in TSMC 28HPC

The Multistandard SerDes is available in TSMC 65nm and GF28SLP process node to support wide range of standards like PCI, SATA, XFI etc.

29
Multi-Link Multi-Protocol SerDes 10Gbps in GF 28SLP

Terminus Circuits offers low power, low latency Multistandard SerDes in TSMC 28nm process node to support wide range of standards like PCI Express, SATA, XFI, USB, XAUI etc.

30
Multi-Link Multi-Protocol SerDes 10Gbps in TSMC 55LP

Terminus Circuits offers low power, low latency Multistandard SerDes in TSMC 28nm process node to support wide range of standards like PCI Express, SATA, XFI, USB, XAUI etc.

31
Multi-Link Multi-Protocol SerDes 10Gbps in TSMC 65GP

Terminus Circuits offers low power, low latency Multistandard SerDes in TSMC 28nm process node to support wide range of standards like PCI Express, SATA, XFI, USB, XAUI etc.

32
PCIe 3.0 Serdes PHY IP, Silicon Proven in TSMC 28HPCP

This Peripheral Component Interconnect Express Gen3 PHY is compliant with PCIe 3.0 Base Specification with support of PIPE 4.3 interface spec. Low power consumption is achieved due to support ...

33
USB 3.0/ PCIe 2.0/ SATA 3.0 Combo PHY IP, Silicon Proven in TSMC 28HPC+

The combination PHY comprises of a Serial ATA (SATA) compliant with the SATA 3.0 Specification, a Peripheral Component Interconnect Express (PCIe) compliant with the PCIe 2.0 Base Specification ...

34
PCIe 4.0 Serdes PHY IP, Silicon Proven in TSMC 12FFC

This Peripheral Component Interconnect Express (PCIe) x4 PHY is compliant with PCIe 4.0 Base Specification with support of PIPE 4.4 interface spec. Lower power consumption is achieved due to ...

35
PCIe 3.1 Serdes PHY IP, Silicon Proven in TSMC 28HPCP

(PCIe 3.1) x4 PHY IP supports PCIe3.1 transmission. This is compliant with PCIe Rev3 Base Specification with support of PIPE 4.3 interface spec. Input clock frequency as 25Mhz, the output data ...

36
PCIe 3.0 Serdes PHY IP, Silicon Proven in UMC 28HPC

This PCIe 3.0 Base Specification-compliant Peripheral Component Interconnect Express Gen3 PHY supports the PIPE 4.3 interface standard. Due to the support of an extra PLL control, reference ...

37
PCIe 3.0 Serdes PHY IP, Silicon Proven in UMC 40LP

This PCIe 3.0 Base Specification-compliant Peripheral Component Interconnect Express Gen3 PHY supports the PIPE 4.3 interface standard. Due to the support of an extra PLL control, reference ...

38
PCIe 3.0 Serdes PHY IP, Silicon Proven in UMC 55SP

The Peripheral Component Interconnect Express Gen3 PHY IP with PIPE 4.3 interface standard supported by this that complies with PCIe 3.0 Base Specification. Low power usage is made possible ...

39
PCIe 3.0 Serdes PHY IP, Silicon Proven in SMIC 14SFP

This Peripheral Component Interconnect Express (PCIe) x4 PHY is compliant with PCIe 3.0 Base Specification with support of PIPE 4.3 interface spec. Lower power consumption is achieved due to ...

40

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