Multiprotocol SerDes PMA supporting variety of interfaces.

1 Testimonial
Lyle Smith, Vice President of Product Development Engineering, Microsemi SoC BU

Multiprotocol SerDes PMA supporting variety of interfaces.

The Controller IP is customer configurable and supports PCIe 6.x/PCIe5.x/PCIe4.x/PCIe3.x/ PCIe2.x/PCIe1.x Specifications. The Controller IP support lane widths from x1 to x16.

The KappaCORE-64 from Alphawave Semi is a CXL™ Controller IP that implements the latest CXL 3.0 spec, which is backward compatible with CXL 2.0 and CXL 1.1 specs. This controller forms a complete ...

KA13UGPEP20ST001 provides a complete PHY layer solution for PCIe1.1/PCIe2.0 (2.5/5.0Gbps) for single lane application. It has a serial interface and PIPE3 compliant digital interface. KA13UGPEP20ST001 ...

Analog Bits Programmable SERDES provides a Physical Media Attachment (PMA) Layer capable of signaling at multiple data rates and supports multi-protocol market needs including a wide range of ...

TERMINUS CIRCUITS PCIe GEN2.0 PHY is high performance, low power, low latency Single & Quad-Lane PCI Express PHY that supports PCI Express protocol and its signalling needs. It has features ...

TERMINUS CIRCUITS PCIe GEN2.0 PHY is high performance, low power, low latency Single & Quad-Lane PCI Express PHY that supports PCI Express protocol and its signalling needs. It has features ...

TERMINUS CIRCUITS PCIe GEN2.0 PHY is high performance, low power, low latency Single & Quad-Lane PCI Express PHY that supports PCI Express protocol and its signalling needs. It has features ...

TERMINUS CIRCUITS PCIe GEN2.0 PHY is high performance, low power, low latency Single & Quad-Lane PCI Express PHY that supports PCI Express protocol and its signalling needs. It has features ...

The USB3.0 Super-Speed / PCI Express Combo PHY is a programmable IP that is compatible with the PHY Interface for PCI Express and USB3.0 Super-Speed Architectures specification. The PHY supports ...

The Innosilicon 5Gbps SERDES PHY is a highly configurable PHY capable of supporting speeds up to 5Gbps within a single lane. For this datasheet, the PHY has been configured to support PCIe2.0/USB3.x ...

The Innosilicon SERDES PHY is a highly configurable PHY capable of supporting speeds up to 25Gbps within a single lane. For this particular datasheet, the PHY has been configured to support ...

The Innosilicon SERDES PHY is a highly configurable PHY capable of supporting speeds up to 25Gbps within a single lane. For this particular datasheet, the PHY has been configured to support ...

USB3PCIE20T28HPCP is a complete USB3.0 and PCIe 2.0 Combo PHY IP solutoin designed for a mobile and data consumer applications in T28nm process. It supports both USB3.0 (1 or 2 ports) and PCIe ...

The PCIe2.0 PHY IP is a fully - featured physical layer (PHY) IP solution for mobile and consumer applications. The PHY IP integrates mixed signal circuits to enable both 2.5GT/s and 5.0GT/s ...

The PCIe2.0 PHY IP is an all-in-one physical layer (PHY) IP solution for mobile and consumer applications. The PHY IP includes mixed-signal circuits to handle both 2.5GT/s and 5.0GT/s data transfer ...

The PCIe2.0 PHY IP is a complete physical layer (PHY) IP solution designed for mobile and consumer applications. Compliant with the PCIe2.0 base specifications, the PHY IP integrates mixed-signal ...

PCIe Gen 2 PHY IP is a physical layer (PHY) IP solution for consumer electronics, that allows for a full featured customization and complies with the PCIe2.0 fundamental specifications while ...

PCIe Gen 2.0 PHY IP is a physical layer (PHY) IP solution for mobile, consumer and Enterprise applications that enable for a well equipped customization and complies with the PCIe2.0 standard ...

The PCIe 2.0 PHY IP presents a configurable physical layer (PHY) IP solution tailored for Consumer Electronics. It combines mixed signal circuits to facilitate data transfer speeds of both 2.5GT/s ...

The full gamut of PCIe 2.0 Base operations is covered by PCIe 2.0 transceiver IP. It conforms to the PIPE 3.0 standard. This IP combines high-speed mixed signal circuits to handle PCIe 2.0 traffic ...

The Combo PHY is a complete USB 3.0 and PCIe 2.0 PHY IP solution designed for a mobile and data consumer applications in TSMC 28nm process. It supports both USB3.0 (1 or 2 ports) and PCIe 2.0 ...

Support multiple-lane application ; Fully comply with PIPE3 interface specification ; Support 2.5 G, 5G serial data rate in PCIe application ; Support 5.0G serial data rate in USB application ; ...

The PHY combo comprises Serial ATA (SATA) compliant with SATA 3.0 Specification, Peripheral Component Interconnect Express (PCIe) compliant with PCIe 2.0 Base Specification supporting PIPE interface ...

The combination PHY comprises of a Serial ATA (SATA) compliant with the SATA 3.0 Specification, a Peripheral Component Interconnect Express (PCIe) compliant with the PCIe 2.0 Base Specification ...

With compliance for PIPE 4.4 interface spec, Peripheral Component Interconnect Express (PCIe) Gen4 PHY IP complies with PCIe 4.0 Base Specification. Capability for additional PLL control, reference ...

The combined PHY complies with the PIPE, Serial ATA, PCIe, USB, USB 3.0, USB 2.0, and PCIe Peripheral Component Interconnect Express interface protocols (USB High-speed and Full speed). Supporting ...

The combo PHY consist of Peripheral Component Interconnect Express (PCIe) compliant with PCIe 3.0 Base Specification with support of PIPE interface spec, Universal Serial Bus (USB) compliant ...

The unified PHY complies with the USB, USB 3.0, Serial ATA, Peripheral Component Interconnect Express (PCIe), and USB 2.0 interface protocols (USB High-speed and Full speed). Supporting additional ...

A physical layer (PHY) IP solution for consumer electronics, the PCIe Gen 2 PHY IP allows for customization. The PHY IP complies with the PCIe2.0 fundamental specifications while integrating ...

The combined PHY complies with the Peripheral Component Interconnect Express (PCIe), Serial ATA, USB, USB 3.0, and USB 2.0 interface protocols (USB High-speed and Full speed). Reduced power ...

The combined PHY complies with USB (USB 3.0, USB 2.0), PCIe (Peripheral Component Interconnect Express), Serial ATA (SATA 3.0 Specification), and PIPE interface protocol (USB High-speed and ...

Serial ATA (SATA) compliant with SATA 3.0 Specification, Peripheral Component Interconnect Express (PCIe) compliant with PIPE interface protocol, and USB compliant with USB 3.0, USB 2.0, make ...

The combination PHY consists of a Serial ATA (SATA) conforming with the SATA 3.0 Specification, a Peripheral Component Interconnect Express (PCIe) compatible with the PIPE interface protocol, ...

The Innosilicon 8Gbps SERDES PHY is a highly configurable PHY capable of supporting speeds up to 8Gbps within a single lane. For this datasheet, the PHY has been configured to support PCIe3.0/USB3.x ...

The Innosilicon PCIe3.0 PHY is a highly configurable PHY capable of supporting speeds up to 8Gbps within a single lane. For this particular datasheet, the PHY has been configured to support ...

The multi-protocol SerDes PHY consist of Peripheral Component Interconnect Express (PCIe) compliant with PCIe 2.0 Base Specification with support of PIPE interface spec, Universal Serial Bus ...

The multi-protocol SerDes PHY consists of Serial ATA (SATA) conforming with SATA 3.0 Specification, Peripheral Component Interconnect Express (PCIe) compliant with PCIe 2.0 Base Specification ...

The multi-protocol SerDes PHY consist of Peripheral Component Interconnect Express (PCIe) compliant with PCIe 2.0 Base Specification with support of PIPE interface spec, Universal Serial Bus ...