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MIPI C-PHY v1.2 D-PHY v2.1 RX 2 trios/2 Lanes in TSMC (16nm,N6, N5)
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DisplayPort Transmitter Link Controller
Our 5th generation DisplayPort Transmitter Link Controller core supports DisplayPort 1.4, 2.0 and embedded DisplayPort 1.4b features, including link rates up to 8.1Gbps, Display Stream Compression (DSC 1.2), multi-stream transport (MST) and more. The base core includes all required link functionality—Main Link, Secondary Channel, and AUX Channel protocols—and supports the HDCP 1.3 and HDCP 2.2 standards for data encryption.
The DisplayPort Transmitter core interfaces use common industry standards for low-complexity integration.
The DisplayPort Transmitter core interfaces use common industry standards for low-complexity integration.
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Block Diagram of the DisplayPort Transmitter Link Controller IP Core
DisplayPort Controller IP
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