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I3C Host Controller v1.2

• Compliant with MIPI I3C Specification v1.2
• Compliant with MIPI I3C HCI Specification v1.1
• Supports up to 12.5 MHz operation using Push-Pull

AV1/HEVC/AVC/VP9 Video Decoder HW IP 8K30fps@500MHz

• High-quality encoding
• Improved bandwidth efficiency
• Low delay encoding

MIPI C-PHY v2.0 D-PHY v2.1 RX for TSMC N6

• Compliant with the MIPI D-PHY specification, v2.1
• 4 Lanes in D-PHY mode up to 6.5Gb/s per lane
• Compliant with the MIPI C-PHY specification, v2.0

Safety Enhanced General Purpose Neural Processing Unit (NPU)

• Hybrid Von Neuman + 2D SIMD matrix architecture
• 64b Instruction word, single instruction issue per clock
• 7-stage, in-order pipeline

Logic based Hardware Root-of-Trust - Physical Unclonable Function (PUF)

• Secure provisioning
• Secured identities
• High entropy seeds

On-Die PDN Analyzer for Transistor-Level Visibility and Telemetry

• Transistor-level PDN visibility
• PDN telemetry and onboard analytics across the silicon lifecycle

10G Base T Ethernet PHY

• CAD Proven database
• Ready to go for fabrication and characterization
• ASIC volume production ( in future)

LPDDR5X/5/4X PHY IP on TSMC N3P

• Low latency, small area, low power
• Compatible with JEDEC standard LPDDR5X, LPDDR5 and LPDDR4X SDRAMs up to 8533 Mbps

Audio Sample Rate Converter

• Studio-Grade Audio Quality
• Scalable and Efficient
• Fast Synchronization

Lightweight Root-of-Trust

• Rapidly implement secure boot and attestation capabilities without significant area, cost, or complexity overhead.
• Prevent malicious software attacks, unauthorized access, and firmware tampering to safeguard critical device functionality.

2kx8 Bits OTP (One-Time Programmable) IP, TSM- 40ULP 1.1/2.5V Process

• Small IP size
• Low program voltage/current
• Low read voltage/current

Dual Port Register File Compiler (1 Read-Only Port, 1 Write-Only Port)

• Ultra Low Standby Current
• .72V to .88V
• Internal Bist Mux

Register File with low power retention mode and 3 speed options

• Ultra-Low Leakage: High VT (HVT) and low leakage HVT (LLHVT) devices used with source biasing to minimize standby currents while operating at low voltage.

UCIe/BoW BlueLynx™ Dual Mode PHY and subsystem IP for chiplet interconnect

• Emerging Standard Knowledge
• Flexibly Configurable
• Best in Class PPA

TSMC FPD-Link / OpenLDI / LVDS forwarded clock SERDES Link

• Universal LVDS-based interfaces supporting variety of Tx and Rx configurations.

13-bit, 80 MSPS Analog-to-Digital Converter IP Block

• 13-bit resolution
• 80 MSPS sampling speed
• Bandwidth: 2 MHz around Fs/4

Image processing specialized NPU

• Highly Optimized for CNN-based Image Processing Application
• Fully Programmable Processing Core
• 16bit Floating Point Arithmetic Unit

MIPI CSI-2

• (SROI) Smart Region of Interest,
• (USL) Universal Serial Link,
• (AOSC) Always-On Sentinel Conduit,

LPDDR5X/5/4X PHY in TSMC (N5, N4P, N3E, N3P, N3A)

UCIe PHY & D2D Adapter

• 32Gbps UCIe-Advanced (UCIe-A) & Standard (UCIe-S)
• UCIe v1.1 specification

Multi-protocol SerDes PMA - PCIe1 PCIe2 PCIe3 PCIe4 PCIe5 and more

• Very wide CDR range -- operates with data rates from 0.25Gbps to 12.7Gbps
• Extremely low jitter suitable for Enterprise SerDes applications

USB4 PHY in TSMC (N7, N6, N5, N4P, N3E, N3P)

PCIe 5.0 PHY IP for TSMC N5

• Physical Coding Sublayer (PCS) block with PIPE interface
• Supports PCIe 5.0, 4.0, 3.1, 2.1, 1.1 encoding, backchannel initialization

7-bit, 64 GSPS ADC Ultra Low Power

• Ultra-high bandwidth time-interleaved ADC
• 7-bit ADC resolution
• Sampling rate up to 64GSPS