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I3C Host Controller v1.2

• Compliant with MIPI I3C Specification v1.2
• Compliant with MIPI I3C HCI Specification v1.1
• Supports up to 12.5 MHz operation using Push-Pull

AV1/HEVC/AVC/VP9 Video Decoder HW IP 8K30fps@500MHz

• High-quality encoding
• Improved bandwidth efficiency
• Low delay encoding

MIPI C-PHY v2.0 D-PHY v2.1 RX for TSMC N6

• Compliant with the MIPI D-PHY specification, v2.1
• 4 Lanes in D-PHY mode up to 6.5Gb/s per lane
• Compliant with the MIPI C-PHY specification, v2.0

Safety Enhanced General Purpose Neural Processing Unit (NPU)

• Hybrid Von Neuman + 2D SIMD matrix architecture
• 64b Instruction word, single instruction issue per clock
• 7-stage, in-order pipeline

Logic based Hardware Root-of-Trust - Physical Unclonable Function (PUF)

• Secure provisioning
• Secured identities
• High entropy seeds

On-Die PDN Analyzer for Transistor-Level Visibility and Telemetry

• Transistor-level PDN visibility
• PDN telemetry and onboard analytics across the silicon lifecycle

10G Base T Ethernet PHY

• CAD Proven database
• Ready to go for fabrication and characterization
• ASIC volume production ( in future)

LPDDR5X/5/4X PHY IP on TSMC N3P

• Low latency, small area, low power
• Compatible with JEDEC standard LPDDR5X, LPDDR5 and LPDDR4X SDRAMs up to 8533 Mbps

Audio Sample Rate Converter

• Studio-Grade Audio Quality
• Scalable and Efficient
• Fast Synchronization

Lightweight Root-of-Trust

• Rapidly implement secure boot and attestation capabilities without significant area, cost, or complexity overhead.
• Prevent malicious software attacks, unauthorized access, and firmware tampering to safeguard critical device functionality.

2kx8 Bits OTP (One-Time Programmable) IP, TSM- 40ULP 1.1/2.5V Process

• Small IP size
• Low program voltage/current
• Low read voltage/current

Dual Port Register File Compiler (1 Read-Only Port, 1 Write-Only Port)

• Ultra Low Standby Current
• .72V to .88V
• Internal Bist Mux

On-Die PDN Analyzer for Transistor-Level Visibility and Telemetry

• Transistor-level PDN visibility
• PDN telemetry and onboard analytics across the silicon lifecycle

High Bandwidth Memory 3 (HBM3/3E) IP optimized for Samsung SF4X

• Supports up to 9.6 Gbps/pin
• Supports 16 channels (32 pseudo channels)
• Supports AXI4 mainband and AXI4-Lite sideband interfaces

Ultra low-power crystal-based 32 kHz oscillator designed in TSMC 12FFC+

• Compatible with 4 pF to 12.5 pF crystals
• Tolerate no load capacitance on the board to minimize the BoM
• FOK signal indicating when the clock signal is ready

Process/Voltage/Temperature Sensor (Supply voltage 1.8V/0.9V)

• UMC 28nm HPC+ technology
• Temperature measurement range -40°C ÷ +125°C

DVB-S2X Wideband LDPC BCH Decoder IP Core

• Improved performance
• Improved efficiency w.r.t. Shannon’s limit
• Finer gradation of code rate and SNR

Temperature/Voltage Sensor IP

Process/Voltage/ Temperature Sensor

12-bit, 4 GSPS High Performance IQ ADC in 22nm FD-SOI

• GF22FDX Process
• 12-bit resolution, 4GSPS update rate
• Dual ADC configured as IQ Pair

JESD204B Controller

PCIe 6.x / PCIe5.x / PCIe4.x / PCIe3.x / PCIe2.x / PCIe1.x Controller

Sleep Management Subsystem

• Power-On-Reset
• Programmable relaxation oscillator
• Low Power Comparator

MIPI C-PHY/D-PHY Combo CSI-2 TX 4.5Gsps/trio in TSMC 28nm

• Dual mode PHY Supports MIPI Alliance Specification D-PHY v2.5 & C-PHY v2.0
• Consists of 1 Clock lane and 4 Data lanes in D-PHY mode
• Consists of 3 Data lanes in C-PHY mode