DDR5/DDR4/LPDDR5 Combo PHY IP - 4800Mbps (Silicon Proven in TSMC 12FFC)
Open source version of the UltraSPARC T1 processor
By making the source for this design available for a larger community to review and learn from, we expect that ideas around the multi-thread concepts can be explored more freely and openly, and that truly beneficial innovations can be achieved.
View Open source version of the UltraSPARC T1 processor full description to...
- see the entire Open source version of the UltraSPARC T1 processor datasheet
- get in contact with Open source version of the UltraSPARC T1 processor Supplier








