USB 3.2 Gen2/Gen1 PHY IP in TSMC(5nm, 6nm, 7nm,12nm/16nm, 22nm, 28nm, 40nm, 55nm)
PCIe 5.0 Controller supporting Endpoint, Root Port, Switch, Bridge and advanced features
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Block Diagram of the PCIe 5.0 Controller supporting Endpoint, Root Port, Switch, Bridge and advanced features

PCIe IP
- PCIe 5.0 Integrity and Data Encryption Security Module
- PCIe 6.1 Controller
- PCIe 5.0 Serdes PHY IP, Silicon Proven in TSMC 12FFC
- Multi-protocol SerDes PMA - PCIe1 PCIe2 PCIe3 PCIe4 PCIe5 and more
- PCIe Gen 6 SERDES IP - supports up to 112G LR ethernet with low power and latency
- 56G Serdes in 7nm bundled with PCie Gen 5 controller IP