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I3C Host Controller v1.2

• Compliant with MIPI I3C Specification v1.2
• Compliant with MIPI I3C HCI Specification v1.1
• Supports up to 12.5 MHz operation using Push-Pull

AV1/HEVC/AVC/VP9 Video Decoder HW IP 8K30fps@500MHz

• High-quality encoding
• Improved bandwidth efficiency
• Low delay encoding

MIPI C-PHY v2.0 D-PHY v2.1 RX for TSMC N6

• Compliant with the MIPI D-PHY specification, v2.1
• 4 Lanes in D-PHY mode up to 6.5Gb/s per lane
• Compliant with the MIPI C-PHY specification, v2.0

Safety Enhanced General Purpose Neural Processing Unit (NPU)

• Hybrid Von Neuman + 2D SIMD matrix architecture
• 64b Instruction word, single instruction issue per clock
• 7-stage, in-order pipeline

Logic based Hardware Root-of-Trust - Physical Unclonable Function (PUF)

• Secure provisioning
• Secured identities
• High entropy seeds

On-Die PDN Analyzer for Transistor-Level Visibility and Telemetry

• Transistor-level PDN visibility
• PDN telemetry and onboard analytics across the silicon lifecycle

10G Base T Ethernet PHY

• CAD Proven database
• Ready to go for fabrication and characterization
• ASIC volume production ( in future)

LPDDR5X/5/4X PHY IP on TSMC N3P

• Low latency, small area, low power
• Compatible with JEDEC standard LPDDR5X, LPDDR5 and LPDDR4X SDRAMs up to 8533 Mbps

Audio Sample Rate Converter

• Studio-Grade Audio Quality
• Scalable and Efficient
• Fast Synchronization

Lightweight Root-of-Trust

• Rapidly implement secure boot and attestation capabilities without significant area, cost, or complexity overhead.
• Prevent malicious software attacks, unauthorized access, and firmware tampering to safeguard critical device functionality.

2kx8 Bits OTP (One-Time Programmable) IP, TSM- 40ULP 1.1/2.5V Process

• Small IP size
• Low program voltage/current
• Low read voltage/current

Dual Port Register File Compiler (1 Read-Only Port, 1 Write-Only Port)

• Ultra Low Standby Current
• .72V to .88V
• Internal Bist Mux

12-bit, 9 GSPS High Performance Swift™ ADC in 16nm CMOS

• 16nm CMOS
• Ultra high-performance low-power ADC
• 12-bit ADC resolution

JESD204D Transmitter and Receiver IP

• Designed according to JEDEC JESD204D Standard.
• Supports up to 24 lanes per IP cores.

2-stage Power Amplifier 39GHz ultra-efficient Dual-Drive™ PA

• Best in class efficiency
• Plug and play
• Frequency and process agnostic

2-stage Power Amplifier 14.5GHz ultra-efficient Dual-Drive™ PA

• 2-stage PAEmax = 50%
• PA-stage DEmax = 60%
• Psat = 20dBm

7-bit, 64 GSPS ADC Ultra Low Power

• Ultra-high bandwidth time-interleaved ADC
• 7-bit ADC resolution
• Sampling rate up to 64GSPS

JESD204D - Succesfully Taped out, Silicon Agnostic IP core

Fractal-D Amplifier

LDO Voltage Regulator, 30 mA, Adjustable 0.45 V to 0.9 V Output

12-bit 12-Gsps ADC

• 12-Gsps peak sample rate
• 12 bit resolution (10-bit option)
• SMALLER than competing solutions

Low Dropout (LDO) Capless Regulator - GF 22FDX

• Input voltage of 1.2V
• Output voltage of 0.8V to 0.95V
• Up to 250mA output current

Low Dropout (LDO) Capless Regulator

2-stage Power Amplifier 28GHz ultra-efficient Dual-Drive™ PA

• 2-stage PAEmax = 52.3%
• PA-stage DEmax = 61.5%
• Psat = 19.02dBm