SATA Device Controller IP Core on Altera Arria II GX

The SATA Device Controller IP Core incorporates the Transport layer, the Link layer, the PHY layer and the Rate Macth FIFO on a ALTERA ARRIA II GX FPGA. The SATA Device Controller IP Core is compliant with Serial ATA II specification and signaling rate is 1.5Gbps and scalable 3Gbs. The SATA Device Controller IP Core is fully synchronous with system frequency (Clock_sys) at 37.5MHz in case of 1.5Gbps speed selection and 75MHz in case of 3Gbs speed selection. The VHDL source code format is available for ease of customization.

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