Semiconductor IP: EFEC with NCG more than 10dB with overhead no more than 20% could be integrated into Xilinx FPGA

EFEC with NCG more than 10dB with overhead no more than 20% could be integrated into Xilinx FPGA

Item #2104

	Posted	Dec. 23, 2022

	# of Offers	5

	Status

		(mail this request to a colleague)

Customer assumes all responsibility for listing this item.

Request Description

Functionality

Enhanced Forward Error Coding, the signal rate is about 10G, and the OH could be 7% or no more than 20%, The codec NCG is greater than 10dB. It is for 10G optical communication.

External compatibility and integration requirements

The IP could be integrated into xilinx or altera environment.

Timing or Performance requirements

seem as the EFEC G975.1 I.7 or G975.1 I.4 in xilinx vivado

Technology Requirements

user interface should be verilog

Availability Timing

4 weeks

Support requirement

Document and testbench.

Quality requirement

Business Scheme Requirement

Bought License

Customer Profile

Position of the person having emitted the request		Business/Corporate Management

Corporation Profile
	End Product	Networking
	Gross Annual Dollar Sales	Under $10 Million
	Size of his organization at this location	20 - 49
	Size of his organization in entire company	50 - 99
	Location	Shanghai, Shanghai, China

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