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aes amba ahb

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Aes amba ahb IP Listing

25 IP Cores

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Advanced Encryption Standard (AES-128) core with AMBA AHB interface

The GRAES core implements the Advanced Encryption Standard (AES) symmetric encryption algorithm for high throughput application (like audio or video streams). The implemented AES-128 algorithm ...

1
Fault Resistant AES Core

AES IP is a AES Engine compliant to NIST FIPS-197 Advanced Encryption Standard. The IP can be programmed to encrypt or decrypt a 128-bit blocks of data using a 128-bit, 192-bit or 256-bit key. ...

2
AES Core

AES IP is a AES Engine compliant to NIST FIPS-197 Advanced Encryption Standard. The IP can be programmed to encrypt or decrypt a 128-bit blocks of data using a 128-bit, 192-bit or 256-bit key. ...

3
AHB AES with DMA

The Advanced Encryption Standard (AES) IP Core is a complete hardware implementation encryption/decryption algorithm described in the U.S. Government Federal Information Processing Standards ...

4
Wireless USB Host Controller

HCL has developed the Device controller for wireless USB which converts the wired USB2.0 device packets to wireless packets based on WUSB specification Rev1.0 thereby maintaining the backward ...

5
Wireless USB Device Controller

HCL has developed the Device controller for wireless USB which converts the wired USB2.0 device packets to wireless packets based on WUSB specification Rev1.0 thereby maintaining the backward ...

6
Configurable AES Core

eSi-AES is a range of sophisticated AES cores for use in ASIC or FPGA technologies. They can be configured to customer the requirements to enable a flexible trade-off of key size, modes and ...

7
AES + SHA DMA Crypto Accelerator

The EIP-120 is a low-power low-gatecount crypto core with DMA capability and local key storage. Compared to a software only solution, the core provides higher performances and additional security ...

8
Advanced Encryption Standard compliant with FIPS 197

AES bridge, a cryptographic coprocessor that complies with FIPS 197 Advanced Encryption Standard, employs the Rijndael encryption method to link APB, AHB, and AXI bus. AES is a block cipher ...

9
Secure AHB Performance Subsystem - ARM M3

The Silvaco Secure AHB Performance Subsystem is a high-performance AHB subsystem that allows for a high level of hardware and software security. It integrates a security conscious processor, ...

10
IP Platform for BLE 5.2 IoT Sensors

The LP1-100 IP Platform is built around the BLE 5.2 connectivity standard. This platform consists of a Bluetooth 5.2 Low Energy Controller and the LP-NNP IP. The LP1-100 IP Platform is designed ...

Evaluation Platform Available

11
IP Platform for AI-Enabled IEEE 802.15.4 Smart Sensors

The LP1-120 IP Platform is built around the IEEE 802.15.4 connectivity standard. This platform consists of the IEEE 802.15.4 MAC and PHY, a sensor fusion IP, and the LP-NNP IP. The LP1-120 IP ...

Evaluation Platform Available

12
IP Platform for Bluetooth 5.2

The LP1-200 IP Platform is built around the Bluetooth 5 connectivity standard. It consists of a Bluetooth 5.2 Low Energy and BR-EDR controllers, an optional low power audio IP and a low power ...

Evaluation Platform Available

13
IP Platform for BLE 5.2 and 802.15.4 IoT Sensors

The LP1-220 IP Platform is built around the BLE 5.2 and 802.15.4 connectivity standards. This platform consists of a Bluetooth 5.2 Low Energy Controller and the 802.15.4 MAC and PHY. It also ...

Evaluation Platform Available

14
SPI FLASH Controller with Execute in place – XIP (SINGLE, DUAL and QUAD SPI Bus Controller with DDR / DTR support and optional AES Encryption)

The DFSPI is a fully configurable SINGLE, DUAL, QUAD and OCTAL SPI master/slave device, which allows user to configure polarity and phase of serial clock signal SCK. As an option, the DFSPI ...

15
Configurable AMBA bus SoC platform

The GRLIB IP Library is an integrated set of reusable IP cores, designed for system-on-chip (SOC) development. The IP cores are centered around the common on-chip bus, and use a coherent method ...

16
Hardened 128-bit Advanced Encryption Standard (AES) coprocessor

The AES Coprocessor encrypts and decrypts 128-bit data blocks by computing an AES algorithm with a 128, 192 or 256-bit key through a highly secure architecture (SPA, DPA[1] and fault hardened). ...

17
Secure-IC's Securyzr™ AES Multi-purpose crypto engine with SCA protections

The AES Crypto Engine IP Core is based on a very flexible wrapper. This wrapper supports a wide selection of programmable ciphering modes: ECB, CTR, CBC, CFB, OFB, OMAC, CCM, GCM, XTS, ... ...

18
IP Platform for Multiprotocol IoT Gateway

The LP1-300 IP Platform is a rich gateway platform for IoT. It consists of a Bluetooth 5.2 Low Energy and BR-EDR Controllers and an 802.15.4 MAC and PHY layers. It also includes a sensor fusion ...

Evaluation Platform Available

19
Secure-IC's Securyzr™ Memory & Bus Protection IP Core

The Memory & Bus Protection IP Core module enables on-the-fly encryption/decryption and authentication to the external memory. It supports AHB/AXI slave/master interfaces, APB port ...

20
Secure-IC's Securyzr™ Inline Decrypter IP Core

The Inline Decrypter IP Core enables on-the-fly execution of encrypted code from Flash. It is often used to protect the source code from decompiling or reverse engineering. This solution ...

21
CAN-SEC Acceleration Engine

Arasan’s CAN-SEC Acceleration Engine Core implements the CAN-XL Protocol (CiA 610-1), CAN-XL Addon Part 1-Simple/Extercontent Indication (CiA 613-1), and CAN-XL Addon Part 2-Security (CiA ...

22
QSPI FLASH Controller – XIP functionality (SINGLE, DUAL and QUAD SPI Bus Controller with Double Data Rate support)

The SPI is a fully configurable SINGLE, DUAL, QUAD and OCTAL SPI master/slave device, which allows user to configure polarity and phase of serial clock signal SCK. The SPI controller is fully ...

23
FSPI Controller – XIP functionality (SINGLE, DUAL, QUAD and OCTAL SPI Bus Controller with Double Data Rate support)

The FSPI is a fully configurable SINGLE, DUAL, QUAD and OCTAL SPI master/slave device, which allows user to configure polarity and phase of serial clock signal (SCK). The FSPI system is flexible ...

24
Secure Boot Hardware Engine

GEON-SBoot is an area-efficient, processor-agnostic hardware engine that protects SoC designs from booting with malicious or otherwise insecure code. The security platform employs public-key ...

25

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