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Ddr4 IP Listing

220 IP Cores (1 - 40)

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DDR4 Memory Controller

Rambus DDR4 Controller Core from Rambus is designed for use in applications requiring high memory throughput, high clock rates and full programmability. The core accepts commands using a ...

1
DDR4/3, LPDDR5x/5/4x/4 Memory Controller IP

OPENEDGES, the memory system IP provider, including DDR memory controller, DDR PHY, on-chip interconnect, and NPU IP together as an integrated solution or independent IP. They are tightly combined ...

2
DDR5/DDR4/LPDDR5 Combo PHY IP - 4800Mbps (Silicon Proven in TSMC 12FFC)

The DDR PHY IP supports DDR5/ DDR4/ LPDDR5, provides low latency, and enables up to 5400MT/s throughput. PHY functionality is verified in NC-Verilog simulation software using test bench written ...

3
High Performance DDR5/4/3 Memory Controller

Mobiveil's DDR5/4/3 Memory Controller is a highly flexible and configurable design targeted for high performance enterprise server and real-time consumer applications that utilize computational ...

4
LPDDR4/3, DDR4/3 Memory Controller IP

OPENEDGES, the memory system IP provider, including DDR memory controller, DDR PHY, on-chip interconnect, and NPU IP together as an integrated solution or independent IP. They are tightly combined ...

5
DDR4 multiPHY in Samsung (14nm)

The Synopsys DDR4 multiPHY is a complete physical (PHY) layer IP interface solution for PC/consumer and mobile ASICs, ASSPs, system-on- chip (SoC), and system-in-package applications requiring ...

6
DDR4 multiPHY in TSMC (28nm)

The Synopsys DDR4 multiPHY is a complete physical (PHY) layer IP interface solution for PC/consumer and mobile ASICs, ASSPs, system-on- chip (SoC), and system-in-package applications requiring ...

7
DDR4/3 PHY in Samsung (14nm, 11nm, 10nm, 8nm)

The Synopsys DDR4/3 PHY is a complete physical layer IP interface (PHY) solution for enterprise-class ASIC, ASSP, and system-on-chip (SoC) applications requiring high-performance DDR4/DDR3/DDR3L ...

8
DDR4/3 PHY in TSMC (12nm, 16nm, 7nm)

The Synopsys DDR4/3 PHY is a complete physical layer IP interface (PHY) solution for enterprise-class ASIC, ASSP, and system-on-chip (SoC) applications requiring high-performance DDR4/DDR3/DDR3L ...

9
DDR4 multiPHY in UMC (28nm)

The Synopsys DDR4 multiPHY is a complete physical (PHY) layer IP interface solution for PC/consumer and mobile ASICs, ASSPs, system-on- chip (SoC), and system-in-package applications requiring ...

10
DDR3/DDR4 IP solution with high performance and low power

With sophisticated architecture and advanced technology, KNiulink provide DDR3/DDR4 IP solution with high performance and low power. KNiulink could offer both controller and PHY IPs. The speed ...

11
DDR3/ 3L/ DDR4/ LPDDR4 PHY, 22nm Technology

The DDR3, DDR3L, DDR4, and LPDDR4 Combo PHY is designed for easy integration into any System-On-Chip (SOC) and can be seamlessly connected to a third-party DFI-compliant DDR3, DDR3L, DDR4, or ...

12
DDR3/3L/DDR4/LPDDR4 PHY

The DDR3, DDR3L, DDR4, and LPDDR4 Combo PHY is designed for easy integration into any System-On-Chip (SOC) and can be seamlessly connected to a third-party DFI-compliant DDR3, DDR3L, DDR4, or ...

13
DDR4 PHY, 16nm/12nm

The DDR4 PHY is designed for easy integration into any System-On-Chip (SOC) and can be seamlessly connected with a third-party DFI-compliant DDR4 memory controller. Depending on the loading ...

14
LPDDR2 / LPDDR3 / DDR3 / DDR3L / DDR3U / DDR4 Combo I/O Pad Set

The LPDDR2/3_DDR3/4 library includes the combo driver/receiver cells with embedded power cells, the driver impedance calibration cell, and a full complement of support cells for both single-ended ...

15
DDR3 / DDR4 Combo I/O Pad Set

The DDR3 / DDR4 library includes the combo driver/receiver cells with embedded power cells, the driver impedance calibration cell, and a full complement of support cells for both single-ended ...

16
LPDDR2 / LPDDR3 / DDR3 / DDR3L / DDR3U / DDR4 Combo I/O Pad Set

The LPDDR2/3_DDR3/4 library includes the combo driver/receiver cells with embedded power cells, the driver impedance calibration cell, and a full complement of support cells for both single-ended ...

17
LPDDR4X/4/DDR4/LPDDR3 Combo PHY & Controller

The INNOSILICON DDR IPTM Mixed-Signal LPDDR4/4X/DDR4/LPDDR3 PHYs provide turnkey physical interface solutions for ICs requiring access to JEDEC compatible SDRAM devices. It is optimized for ...

18
DDR4/3/LPDDR4X/4/3 Combo PHY & Controller

The INNOSILICON DDR IPTM Mixed-Signal DDR4/3/LPDDR4/4X/3 COMBO PHYs provide turnkey physical interface solutions for ICs requiring access to JEDEC compatible SDRAM devices. It is optimized for ...

19
DDR4/LPDDR4/3 Combo PHY & Controller

The INNOSILICON DDR IPTM Mixed-Signal DDR4/LPDDR4/3 COMBO PHYs provide turnkey physical interface solutions for ICs requiring access to JEDEC compatible SDRAM devices. It is optimized for low ...

20
DDR4/3/LPDDR4/3 Combo PHY & Controller

The INNOSILICON DDR IPTM Mixed-Signal DDR4/3/LPDDR4/4X/3 COMBO PHYs provide turnkey physical interface solutions for ICs requiring access to JEDEC compatible SDRAM devices. It is optimized for ...

21
DDR4/3/3L/LPDDR3 Combo PHY & Controller

The INNOSILICON DDR IPTM Mixed-Signal DDR4/3/3L/LPDDR3 COMBO PHYs provide turnkey physical interface solutions for ICs requiring access to JEDEC compatible SDRAM devices. It is optimized for ...

22
DDR4/LPDDR4/4X/3 Combo PHY & Controller

The INNOSILICON DDR IPTM Mixed-Signal DDR4/LPDDR4/4X/3 COMBO PHYs provide turnkey physical interface solutions for ICs requiring access to JEDEC compatible SDRAM devices. It is optimized for ...

23
DDR4/LPDDR4X/4 Combo PHY & Controller

The INNOSILICON DDR IPTM Mixed-Signal LPDDR4/4X/DDR4 PHYs provide turnkey physical interface solutions for ICs requiring access to JEDEC compatible SDRAM devices. It is optimized for low power ...

24
DDR4/3/LPDDR3 Combo PHY & Controller

The INNOSILICON DDR IPTM Mixed-Signal DDR4/3/LPDDR3 COMBO PHYs provide turnkey physical interface solutions for ICs requiring access to JEDEC compatible SDRAM devices. It is optimized for low ...

25
DDR4/3/2 Combo PHY & Controller

The INNOSILICON DDR IPTM Mixed-Signal DDR4/3/2 PHYs provide turnkey physical interface solutions for ICs requiring access to JEDEC compatible SDRAM devices. It is optimized for low power and ...

26
DDR4/3 Combo PHY & Controller

The INNOSILICON DDR IPTM Mixed-Signal DDR4/3 COMBO PHYs provide turnkey physical interface solutions for ICs requiring access to JEDEC compatible SDRAM devices. It is optimized for low power ...

27
PSRAM PHY

The INNOSILICON DDR IPTM Mixed-Signal PSRAM PHY provides turnkey physical interface solutions for ICs requiring access to JEDEC compatible PSRAM devices. It is optimized for low power and high ...

28
DDR 4/3 Memory Controller IP - 2400MHz

This memory controller supports DDR3/4 SDRAM. DDR3/4 memory controller is a high-speed interface used for data read/write between internal engine and outside SDRAM bus, and transfers the internal ...

29
Input 800M-1600MHz, output 800M-1600MHz, all digital DLL for DDR4 SDRAM controller usage, supports slave delay line to generate 25%/50%/100% delay in period of FREF,UMC 40nm Logic Process.

Input 800M-1600MHz, output 800M-1600MHz, all digital DLL for DDR4 SDRAM controller usage, supports slave delay line to generate 25%/50%/100% delay in period of FREF,UMC 40nm Logic Process.

30
Input 333M-1600MHz, output 333M-1600MHz, all digital DLL for DDR4 SDRAM controller usage, supports slave delay line to generate 25%/50%/100% delay in period of FREF,UMC 28nm Logic and Mixed-Mode HPC Process.

Input 333M-1600MHz, output 333M-1600MHz, all digital DLL for DDR4 SDRAM controller usage, supports slave delay line to generate 25%/50%/100% delay in period of FREF,UMC 28nm Logic and Mixed-Mode ...

31
This IP for DDR4, Input 200MHz - 800MHz, output clock_1X 200MHz - 800MHz, output clock_2X 400MHz - 1600MHz, output,frequency synthesizable PLL; UMC 40nm LP Logic Process

This IP for DDR4, Input 200MHz - 800MHz, output clock_1X 200MHz - 800MHz, output clock_2X 400MHz - 1600MHz, output,frequency synthesizable PLL; UMC 40nm LP Logic Process

32
Command/Address Block of DDR3/DDR4/LPDDR2/LPDDR3 Combo PHY for Solder bump Flip chip version ; UMC 40nm LP LowK Logic Process

Command/Address Block of DDR3/DDR4/LPDDR2/LPDDR3 Combo PHY for Solder bump Flip chip version ; UMC 40nm LP LowK Logic Process

33
Data Block of DDR3/DDR4/LPDDR2/LPDDR3 Combo PHY for Solder bump Flip chip version ; UMC 40nm LP LowK Logic Process

Data Block of DDR3/DDR4/LPDDR2/LPDDR3 Combo PHY for Solder bump Flip chip version ; UMC 40nm LP LowK Logic Process

34
Command/Address Block of DDR3/DDR4/LPDDR2/LPDDR3 Combo PHY supporting 2-rank application for Copper Pillar Bump Flip Chip Version; UMC 40nm LP LVT/RVT LowK Logic Process

Command/Address Block of DDR3/DDR4/LPDDR2/LPDDR3 Combo PHY supporting 2-rank application for Copper Pillar Bump Flip Chip Version; UMC 40nm LP LVT/RVT LowK Logic Process

35
Data Block of DDR3/DDR4/LPDDR2/LPDDR3 Combo PHY for copper pillar bump Flip chip version ; UMC 40nm LP LowK Logic Process

Data Block of DDR3/DDR4/LPDDR2/LPDDR3 Combo PHY for copper pillar bump Flip chip version ; UMC 40nm LP LowK Logic Process

36
DFI3.1 Wrapper for DDR3/DDR4/LPDDR2/LPDDR3 PHY

DFI3.1 Wrapper for DDR3/DDR4/LPDDR2/LPDDR3 PHY

37
SDRAM DDR4/3/2 Host Controller & PHY

Dolphin Technology offers high performance DDR4/3/2 SDRAM and LPDDR4/3/2 SDRAM Memory Controller IP across a broad range of process technologies. These Memory Controllers are fully compliant ...

38
DDR4 Controller IP

DDR4 is full-featured, easy-to-use, synthesizable design, compatible with DDR4 JESD79-4, JESD79-4A, JESD79-4A_r2, JESD79-4B, JESD79-4C and JESD79-4D (Draft) specification and DFI-version 3.0 ...

39
DDR4 Controller

The Xilinx DDR4 controller is high performance (2667Mbps in UItraScale+) and supports a wide range of configurations from low cost components to dense 128GB RDIMMs.

40

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