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dma engine

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Dma engine IP Listing

153 IP Cores (1 - 40)

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Multi-Protocol Crypto Packet Engine, Low Power, Bus Attached

The EIP-93 is a Multi-Protocol Engine. The EIP-93 is designed to off-load the host processor to improve the speed of protocol operations and reduce power in cost-sensitive networking products, ...

1
Multi-Protocol Crypto Engine

The EIP-97 is a Cryptographic Engine designed to offload the Host processor to improve the speed of IPsec ESP, IPsec AH, SRTP, SSL, TLS, DTLS and MACsec protocol operations and reduce power ...

2
PCIe 5.0 Controller with AMBA AXI interface

Rambus PCIe 5.0 Controller is a configurable and scalable PCIe controller Soft IP designed for ASIC and FPGA implementation. Rambus PCIe 5.0 Controller is compliant with the PCI Express 5.0 ...

1 Testimonial
Russel Lindsay, Sr. Product Manager, Anritsu Corporation

3
Multi-Protocol Engine with Classifier, Look-Aside, 5-10 Gbps

The Protocol-IP-196 Multi-Protocol Engine is a protocol-aware packet engine for accelerating IPSec, SSL/TLS, DTLS, 3GPP and MACsec up to 10 Gbps in multi-core application or communication processors ...

4
Lancero Scatter-Gather DMA Engine for PCI Express

The Scatter-Gather DMA Engine IP Core for PCI Express provides either a Target Bridge or a Descriptor Bridge SGDMA solution for PCI Express endpoints. The Scatter-Gather DMA Engine connects ...

5
Secure-IC's Securyzr(TM) SM4 Crypto Engine

The SM4 crypto engine includes a generic & scalable implementation of the SM4 algorithm which is the block cipher standard of China. It is compliant with the GBT.32907-2016 specification ...

6
TFT/LCD/MIPI Display Controller and Composition Engine

NEMA®|dc is a powerful display controller which contains several smart tools and functionalities to compose multiple graphics and video layers by improving image quality and contributing significantly ...

1 Testimonial
Dan Cermak, VP of Architecture and Product Planning, Ambiq

7
AMBA Parameter Configurable Multi-Channel DMA Controller (typically up to 1024)

The Multi-Channel DMA Controller supports 1 – 32 independent data block / packet / stream transfers. The Direct Memory Access (DMA) Controller IP Core contains 1 - 32 DMA Controller Engines ...

8
AHB Multi-Channel DMA Controller

The Digital Blocks DB-DMAC-MC-AHB Verilog RTL IP Core is a Multi-Channel DMA Controller supporting 1 – 16 independent data transfers. The Direct Memory Access (DMA) Controller IP Core contains ...

9
DMA AXI4-Stream to/from AXI4 Memory Map - Scatter-Gather Descriptor List

The Digital Blocks DB-DMAC-MC2-DL-MM2S-S2MM Verilog RTL IP Core is a Multi-Channel Scatter-Gather DMA Controller that transfers data between AXI4 Memory Map and AXI4-Stream Interfaces. Control ...

10
DMA AXI4-Stream to/from AXI4 Memory Map - Scatter-Gather Command Stream List

The Digital Blocks DB-DMAC-MC2-CS-MM2S-S2MM Verilog RTL IP Core is a Multi-Channel Scatter-Gather DMA Controller that transfers data between AXI4 Memory Map and AXI4-Stream Interfaces. Control ...

11
Secure-IC's Securyzr™ SHA-3 Crypto Engine

The SHA-3 crypto engine has integrated flexibility and scalability to allow for high throughput and a configurable number of hashing rounds per clock cycle to optimize the silicon resource/performance ...

12

Secure-IC's Securyzr™ ChaCha20-Poly1305 Crypto Engine

The ChaCha20-Poly1305 Crypto Engine is RFC7539 compliant to provide Authenticated Encryption with Associated Data (AEAD) using the ChaCha20 stream cipher combined with the Poly1305 message-authentication ...

13

MACsec Protocol Engine for 10/100/1000 Ethernet

The MAC-SEC-1G IP core implements a compact and configurable custom-hardware protocol engine for the IEEE 802.1AE (MACsec) standard. It supports all cipher suites provisioned by the MACsec standard ...

14

AES supporting ECB, CBC and XTS/XEX modes. Includes DMA and AXI interface.

This is a high performance, small footprint crypt/decrypt IP Core. It features up to 8 independent crypt engines. Three DMA engines make sure the core is always provided with a constant data ...

15

HASH Core, providing MD5, SHA1 and SHA256. Includes DMA and AXI Interface

This is a high performance, small footprint HASH IP Core. It supports three HASH algorithms: MD5, SHA1, SHA256. A S/G DMA engine keeps the core running. Each hash engine has it’s own dedicated ...

16

ZLIB compatible compression and decompession, with DMA and AXi interface

This is a high performance, small footprint ZLIB compatible IP Core. It features 3 DMA engines, AXI interconnect and separate clocks for AXI interfaces and compression/decompression engines.

17

Hash Crypto Engine

With a flexible wrapper supporting a wide selection of programmable hashing modes (SHA-1, SHA-224, SHA-256, SHA-384, SHA-512 and MD-5) and several options of data interface, the Hash crypto ...

18

ZUC Crypto Engine

The ZUC IP core is 3GPP confidentiality and integrity algorithms (EEA3/EIA3) stream cipher for telecommunication applications, requiring high performance with reduced silicon resources. It ...

19

KASUMI Crypto Engine

The KASUMI IP core is 3GPP confidentiality and integrity algorithms (UEA1/UIA1) stream cipher for telecommunication applications, requiring high performance with reduced silicon resources. ...

20

SNOW3G Crypto Engine

The SNOW3G IP core is 3GPP confidentiality and integrity algorithms (UEA2/UIA2) stream cipher for telecommunication applications, requiring high performance with reduced silicon resources. ...

21

SHA-384 and SHA-512 Secure Hash Crypto Engine

The SHA-384/512 is a high-throughput, and compact hardware implementation of the SHA-384 and the SHA-512 cryptographic hash functions provisioned by the FIPS180-4 standard. The core is designed ...

22

AXI4 Multi-Channel DMA Controller (fixed 2,4,8,16 DMA Channels)

The Digital Blocks DB-DMAC-MC-AXI Verilog RTL IP Core is a Multi-Channel DMA Controller supporting 2, 4, 8, or 16 independent data transfers. The Direct Memory Access Controller IP Core contains ...

23

Secure-IC's Securyzr™ AES Multi-purpose crypto engine with SCA protections

The AES Crypto Engine IP Core is based on a very flexible wrapper. This wrapper supports a wide selection of programmable ciphering modes: ECB, CTR, CBC, CFB, OFB, OMAC, CCM, GCM, XTS, ... ...

24

3DES Crypto Engine

The DES / 3-DES IP core implements the Data Encryption Standard (DES / 3DES )according to Federal Information Processing Standards publication 46-3 the (FIPS 46-3) of the National Institute ...

25

PCIe 3.0, 2.1, 1.1 Controller supporting Root Port, Endpoint, Dual-mode Configurations, with AMBA AXI User Interface

Rambus PCIe 3.0 with AXI is a configurable and scalable PCIe controller Soft IP designed for ASIC and FPGA implementation. Rambus PCIe 3.0 with AXI is compliant with the PCI Express 3.1/3.0 ...

1 Testimonial
Murthy Kompella, VP of Engineering, Kazan Networks

26

AES + SHA DMA Crypto Accelerator

The EIP-120 is a low-power low-gatecount crypto core with DMA capability and local key storage. Compared to a software only solution, the core provides higher performances and additional security ...

27

Secure-IC's Securyzr™ ARIA Crypto Engine

The ARIA crypto engine includes a generic implementation of the ARIA algorithm which is the block cipher standard of South Korea. It is compliant with the RFC 6209 specification and ...

28

AHB Triple DES with DMA

The AHB DES/TDES Encryption/Decryption Engine is a configurable core that interfaces to an AHB microprocessor bus. The Controller encrypts or decrypts blocks of data based on the DES encryption ...

29

AHB AES with DMA

The Advanced Encryption Standard (AES) IP Core is a complete hardware implementation encryption/decryption algorithm described in the U.S. Government Federal Information Processing Standards ...

30

DMA Controller with AHB IP

DMA Controller with AHB interface is full featured, easy-to-use, synthesizable design that can be used with AHB based systems as a controller to transfer data directly from system memory to ...

31

DMA Controller with AXI IP

DMA Controller with AXI interface is full featured, easy-to-use, synthesizable design that can be used with AXI based systems as a controller to transfer data directly from system memory to ...

32

USB 2.0 Serial Interface Engine with UTMI

The USB 2.0 Controller provides a high and full speed USB function interface to an embedded system. The USB 2.0 Controller implements a full USB 2.0 interface at a rate of 480Mbits/s and ...

33

AXI Central DMA Controller

The Xilinx LogiCORE™ IP AXI Central Direct Memory Access (CDMA) core is a soft Xilinx Intellectual Property (IP) core for use with the Vivado® Design Suite. The AXI CDMA provides high-bandwidth ...

34

AXI DMA Controller

The AXI Direct Memory Access (AXI DMA) IP provides high-bandwidth direct memory access between memory and AXI4-Stream-type target peripherals. Its optional scatter gather capabilities also offload ...

35

AXI Video DMA (AXI VDMA)

The AXI Video Direct Memory Access (AXI VDMA) core is a soft Xilinx IP core that provides high-bandwidth direct memory access between memory and AXI4-Stream type video target peripherals. The ...

36

DMA for PCI Express (PCIe) Subsystem

The Xilinx® LogiCORE™ DMA for PCI Express® (PCIe) implements a high performance, configurable Scatter Gather DMA for use with the PCI Express Integrated Block. The IP provides an optional ...

37

Synthesized RTL of Cryptographic DMA (RMACE) IP-core

• AXI master interface ; • Built-in scatter-gather DMA engine ; • Support modes: ; • pass-through (direct) ; • permutation by preset scheme ; • logic XOR up to 255 operands ; • AES-128 ...

38

Hardware Offload Engine for 1394b AS5643

The New Wave Design and Verification (New Wave DV) 1394b AS5643 IP core provides a complete hardware IP solution for the 1394b AS5643 protocol. The core provides hardware based AS5643 message ...

39

Parallel ATA IP Host Controller with Integrated DMA

The Mentor Graphics?parallel ATA host interface controller provides an efficient and easy-to-use interface to IDE and ATAPI devices. The core implements programmable I/O, multi-word direct memory ...

40

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