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Lin controller IP Listing

860 IP Cores (1 - 40)

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Compute Express Link (CXL) 3.1 Controller

The Rambus Compute Express Link® (CXL®) 3.1 controller is a parameterizable design for ASIC and FPGA implementations. It leverages the Rambus PCIe® 6.1 controller architecture for the CXL.io ...

1
Ceva-Waves Bluetooth 5.4 Low Energy Baseband Controller / Link Layer, software and profiles

Ceva-Waves Bluetooth 5.4 Low Energy IP is a comprehensive and flexible solution for integration into SoCs/ASSPs. The Ceva-Waves BLE hardware baseband controller core, in charge of packet ...

2
Bluetooth low energy v6.0 Baseband Controller, Protocol Software Stack and Profiles IP

This Software and Silicon IP solutions, feature Bluetooth v6.0 capabilities including a certified Link-layer controller, Digital PHY, Stack & Profiles. Endorsed by the Bluetooth Special Interest ...

3
Compute Express Link (CXL) 2.0 Controller

Rambus Compute Express Link (CXL) 2.0 Controller leverages a silicon-proven PCIe 5.0 controller architecture for the CXL.io path, and adds CXL.cache and CXL.mem paths specific to the CXL standard. ...

4
Compute Express Link (CXL) 2.0 Controller with AMBA AXI interface

Rambus CXL 2.0 Controller with AXI is a parameterizable Compute Express Link (CXL) controller Soft IP designed for ASIC and FPGA implementation. Rambus CXL 2.0 Controller with AXI leverages ...

5
Bluetooth low energy v5.4 Baseband Controller, Protocol Software Stack and Profiles IP

This Software and Silicon IP solutions, feature Bluetooth v5.4 capabilities including a certified Link-layer controller, Digital PHY, Stack & Profiles. Endorsed by the Bluetooth Special Interest ...

6
Ceva-Waves Bluetooth 5.3 Low Energy Baseband Controller, software and profiles

Ceva-Waves Bluetooth 5.3 Low Energy IP is a comprehensive and flexible solution for integration into SoCs/ASSPs. The Ceva-Waves BLE hardware baseband controller core, in charge of packet ...

7
Compute Express Link (CXL) 1.1/2.0/3.0 Controller

The KappaCORE-64 from Alphawave Semi is a CXL™ Controller IP that implements the latest CXL 3.0 spec, which is backward compatible with CXL 2.0 and CXL 1.1 specs. This controller forms a complete ...

8
LINFlexD Controller

The LINFlexD Controller is a serial communication interface designed for Local Interconnect Network (LIN) applications. The LINFlexD manages a high number of LIN messages efficiently with a ...

9
DisplayPort Transmitter Link Controller

Our 5th generation DisplayPort Transmitter Link Controller core supports DisplayPort 1.4, 2.0 and embedded DisplayPort 1.4b features, including link rates up to 8.1Gbps, Display Stream Compression ...

10
DisplayPort Receiver Link Controller

Our 5th generation DisplayPort Receiver Link Controller core supports DisplayPort 1.4, 2.0 and embedded DisplayPort 1.4b features, including link rates up to 8.1 Gbps. The highly integrated ...

11
Host / Device LIN controller

Arasan’s LIN Controllers IP– Local Interconnect Network Controllers IPs are compliant to LIN 2.0, 2.1 & 2.2A Specifications. Backward compliant to LIN 1.3 Specification as well. These can ...

12
LIN Bus Master/Slave Controller Core

Implements a communication controller that transmits and receives complete Local Interconnect Network (LIN) frames to perform serial communication according to the LIN Protocol Specification. ...

13
Highly configurable high-speed serial link controller

The GRHSSL IP is a highly configurable high-speed serial link controller, described in VHDL. It can implement: * SpaceFibre controller (GRSPFI) * WizardLink controller (GRWIZL) * ...or ...

14
LIN Master Slave Controller

Local Interconnect Network (LIN) is a broadcasting, Single Master, and Multi Slave (up to 16) communication protocol designed to support those features where CAN is not required.

15
LIN Bus Controller – Basic and Safety-Enhanced

DCD-SEMI believes that even though something may be small or slow, it can still offer maximal efficiency and ultimate reliability. That’s why our DLIN controller with UART half-duplex enhanced ...

2 Testimonials
Alex Chen, Project Leader of Business Project Department, Faraday Technology Corporation

16
ZYNQ SATA 3 AHCI Host Controller with Linux Driver

The LDS SATA 3 HOST AHCI XZ7 IP incorporates the AHCI registers model, the Transport layer, the Link layer and the PHY layer on a Xilinx Zynq speed grade 2 FPGA. The LDS_SATA 3 HOST AHCI XZ7 ...

17
MIPI D-PHY TX/CSI2 Link Controller

CD12631S4TIP is a link IP that allows you to link a camera module or CMOS image sensor (CIS) to a host system. This LINK IP is a soft macro IP that has the function of converting input data ...

18
Multi-PHY Receiver Link Controller

CD12842M8LRM3BM4AIP312P5 is a link IP that allows you to link a camera module or CMOS image sensor (CIS) to a host system. This LINK IP is a soft macro IP that has the function of converting ...

19
Universal Chiplet Interconnect Express (UCIe) Controller

Synopsys UCIe Controller IP is comprised of the Die-to-Die Adapter layer and Protocol layer for widely used protocols such as PCI Express and CXL. The IP also enables latency-optimized NoC-to-NoC ...

20
1.6T Ultra Ethernet IP Solution with PHY, Controller and Verification IP

The Synopsys 1.6T Ultra Ethernet IP solution, consisting of 1.6T MAC and PCS multi-rate Ethernet controllers, silicon-proven 224G Ethernet PHY IP, and verification IP, is designed to meet the ...

21
GDDR7 Memory Controller

The Rambus GDDR7 controller core is designed for use in applications requiring high memory throughput including graphics, high performance computing (HPC), and artificial intelligence/machine ...

22
HDMI ver1.3 Receiver IP

HDMI Receiver Link IP Core supporting the standard of HDMI 1.3a, which will be quickly implemented into SoC of consumers; product (HD-TV, AV receiver... etc.). The best performance, efficiency ...

23
HDMI ver1.3 Transmitter IP

HDMI Transmitter Link IP Core supporting the standard of HDMI 1.3a which will be quickly implemented into SoC of consumers' product (HD-TV, AV receiver... etc.). The best performance, efficiency ...

24
LIN 2.2, 2.1 and 1.3 Protocol Controller IP

The LIN is a soft core of the Local Interconnect Network (LIN). This interface is a serial communication protocol, designed primarily to be used in automotive applications. Compared to CAN, ...

25
Bluetooth Dual Mode v5.3 Baseband Controller IP

This Baseband Controller IP core is a composite HW-FW implementation of the Classic Bluetooth specifications and Bluetooth Low Energy v5.3 Specifications. Compatible with the standard Bluetooth ...

26
Local Interconnect Network (LIN) Soft Controller IP

The DLIN is a soft core of the Local Interconnect Network (LIN). This interface is a serial communication protocol, primarily designed to be used in automotive applications. Compared to the ...

27
Display Port v1.4 Tx PHY & Controller IP, Silicon Proven in TSMC 12FFC

The DisplayPort v1.4 Tx PHY IP in 12FFC is a modernistic technology designed to be integrated into chip designs for various devices, including graphics cards, monitors, and laptops. Utilizing ...

28
APB Fundamental Peripheral IP, Serial Interface controller for multiple frame formats, SSP (by TI), SPI (by Motorola), Microwire (by NS), I2S (by Philips), AC - link (by Intel) and SPDIF (by Intel), Soft IP

Synchronous serial port interface controller with APB interface.

29
Input 800M-1600MHz, output 800M-1600MHz, all digital DLL for DDR4 SDRAM controller usage, supports slave delay line to generate 25%/50%/100% delay in period of FREF,UMC 40nm Logic Process.

Input 800M-1600MHz, output 800M-1600MHz, all digital DLL for DDR4 SDRAM controller usage, supports slave delay line to generate 25%/50%/100% delay in period of FREF,UMC 40nm Logic Process.

30
Input 333M-1600MHz, output 333M-1600MHz, all digital DLL for DDR4 SDRAM controller usage, supports slave delay line to generate 25%/50%/100% delay in period of FREF,UMC 28nm Logic and Mixed-Mode HPC Process.

Input 333M-1600MHz, output 333M-1600MHz, all digital DLL for DDR4 SDRAM controller usage, supports slave delay line to generate 25%/50%/100% delay in period of FREF,UMC 28nm Logic and Mixed-Mode ...

31
InCore Calcite Series: 32b/64b RISC-V 5-stage, scalar, in-order, Application Processor. Linux and multi-core capable. Maps upto ARM A-35. Optimal PPA.

InCore Calcite is a 32/64 Bit RISC-V in-order, single-issue 5-stage pipelined micro-processor. Built on Incore's proprietary deep-customization stack for microarchitectural exploration, Calcite ...

32
LIN Controller IP

LIN interface provides full support for the LIN synchronous serial interface, compatible with LIN 2.2A specification. Through its LIN compatibility, it provides a simple interface to a wide ...

33
Link Layer Controller

Fully compliant with IEEE 1394-1995 Standards. . ; Half Duplex Independent; Transmit and Receive Data Path controlled by Rx Tx Controller. ; 32-bit Generic Host Bus Interface. ; Has a hand-shaking ...

34
Synchronous Data Link Controller

CoreSDLC provides a high-speed synchronous serial communication controller that utilizes the synchronous data link control (SDLC) protocol. Operation of the CoreSDLC controller is similar ...

35
1394b FPGA Link Layer Controller

The FireCore Basic is targeted for applications with up to S3200 data transmission requirements and for designs with a non-PCI Link Controller requirement. FireCore was designed to meet the ...

36
FireLink IEEE1394b Link Layer Controller

The synthesizable IEEE1394b Link Layer Controller Core, FireLink®, is based on the Link Layer Controller that has been used for several years in the FireSpy® analyzers produced by DapTechnology. ...

37
Bluetooth 5.2 / 5.1 / 5.0 / 4.2 LE Controller with Link Layer and optional 802.15.4 MAC

Packetcraft's Bluetooth 5.2 / 5.1 / 5.0 / 4.2 Low Energy Controller IP, (PC-BLE-C5.2), is a highly optimized, comprehensive and flexible solution for integration into SoCs/ASSPs. Offered in ...

Evaluation boards available

38
Bluetooth 5.3 LE Controller with Link Layer and optional 802.15.4 MAC

Packetcraft's Bluetooth 5.3 Low Energy Controller IP, (PC-BLE-C5.3), is a highly optimized, comprehensive and flexible solution for integration into SoCs/ASSPs. Offered in full source code form, ...

Evaluation boards available

39
Bluetooth 5.4 LE Controller with Link Layer, optional 802.15.4 MAC, early access to Channel Sounding

Packetcraft's Bluetooth 5.4 Low Energy Controller IP, (PC-BLE-C5.4), is a highly optimized, comprehensive and flexible solution for integration into SoCs/ASSPs. Offered in full source code form, ...

40

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