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Pci controller ip IP Listing

274 IP Cores (1 - 40)

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PCIe 6.1 Controller

The Rambus PCI Express® (PCIe®) 6.1 Controller is a configurable and scalable design for ASIC implementations. It is backward compatible to the PCIe 5.0, 4.0 and 3.1/3.0, as well as version ...

1
Compute Express Link (CXL) 3.1 Controller

The Rambus Compute Express Link® (CXL®) 3.1 controller is a parameterizable design for ASIC and FPGA implementations. It leverages the Rambus PCIe® 6.1 controller architecture for the CXL.io ...

2
PCIe 7.0 Controller

The Rambus PCI Express® (PCIe®) 7.0 Controller is a configurable and scalable design for ASIC implementations. It is backward compatible to the PCIe 6.0 and 5.0, as well as version 6.2.1 PHY ...

3
PCIe 7.0 Controller with AXI

The Rambus PCI Express® (PCIe®) 7.0 Controller with AXI is a configurable and scalable design for ASIC implementations. It is backward compatible to PCIe 6.2 and 5.0, and compatible with version ...

4
PCIe 7.0 Retimer Controller

The Rambus PCI Express® (PCIe®) 7.0 Retimer Controller provides a complete digital data path solution that delivers best-in-class latency, power and area, and accelerates the time-to-market ...

5
56G Serdes in 7nm bundled with PCie Gen 5 controller IP

New IP for value conscious designers. Integrates Serdes for high speed Ethernet and PCIe (to Gen5). Also bundled with PCie Gen 5 controller reduces costs and risks

6
Compute Express Link (CXL) 2.0 Controller

Rambus Compute Express Link (CXL) 2.0 Controller leverages a silicon-proven PCIe 5.0 controller architecture for the CXL.io path, and adds CXL.cache and CXL.mem paths specific to the CXL standard. ...

7
Compute Express Link (CXL) 2.0 Controller with AMBA AXI interface

Rambus CXL 2.0 Controller with AXI is a parameterizable Compute Express Link (CXL) controller Soft IP designed for ASIC and FPGA implementation. Rambus CXL 2.0 Controller with AXI leverages ...

8
PCIe 5.0 Controller supporting Endpoint, Root Port, Switch, Bridge and advanced features

Rambus PCIe 5.0 Controller is a configurable and scalable PCIe controller Soft IP designed for ASIC and FPGA implementation. Rambus PCIe 5.0 Controller is compliant with the PCI Express 5.0 ...

2 Testimonials
June Paik, CEO, Furiosa

9
PCIe 5.0 Controller with AMBA AXI interface

Rambus PCIe 5.0 Controller is a configurable and scalable PCIe controller Soft IP designed for ASIC and FPGA implementation. Rambus PCIe 5.0 Controller is compliant with the PCI Express 5.0 ...

1 Testimonial
Russel Lindsay, Sr. Product Manager, Anritsu Corporation

10
PCIe Controller Testbench

PCIe Testbench from Rambus emulates a Root Complex device enabling simulation of a PCI Express design. This includes the following features: • Root Complex master requests are generated ...

11
PCIe 4.0 Controller supporting Endpoint, Root Port, Switch, Bridge and advanced features

Rambus PCIe 4.0 Controller is a configurable and scalable PCIe controller Soft IP designed for ASIC and FPGA implementation. The Rambus PCIe 4.0 Controller is compliant with the PCI Express ...

12
PCIe 4.0 Controller with AMBA AXI interface

Rambus PCIe 4.0 Controller is a configurable and scalable PCIe controller Soft IP designed for ASIC and FPGA implementation. The Rambus PCIe 4.0 Controller is compliant with the PCI Express ...

13
PCIe 5.0 Serdes PHY IP, Silicon Proven in TSMC 12FFC

This Peripheral Component Interconnect Express (PCIe) x4 PHY is compliant with PCIe 5.0 Base Specification with support of PIPE 5.1 interface spec. Lower power consumption is achieved due to ...

14
PCIe 6.x / PCIe5.x / PCIe4.x / PCIe3.x / PCIe2.x / PCIe1.x Controller

The Controller IP is customer configurable and supports PCIe 6.x/PCIe5.x/PCIe4.x/PCIe3.x/ PCIe2.x/PCIe1.x Specifications. The Controller IP support lane widths from x1 to x16.

15
Compute Express Link (CXL) 1.1/2.0/3.0 Controller

The KappaCORE-64 from Alphawave Semi is a CXL™ Controller IP that implements the latest CXL 3.0 spec, which is backward compatible with CXL 2.0 and CXL 1.1 specs. This controller forms a complete ...

16
PCIE Gen5 digital controller

Primeexpress PCIE Gen5 digital controller from Primesoc, is well architect,high performance, modular designed and tailor made to plug and play in SOCs. Primeexpress can be configured to work ...

17
PCI Express (PCIe) 5.0 Controller

Application-optimized, high-performance controller IP for PCIe The Cadence® Controller IP for PCIe 5.0 provides the logic required to integrate a root complex (RC), endpoint (EP), or ...

18
PCI Express (PCIe) 4.0 Controller

Application-optimized, high-performance controller IP for PCIe The Cadence® Controller IP for PCIe 4.0 provides the logic required to integrate a root complex (RC), endpoint (EP), or ...

19
PCI Express (PCIe) 3.1 Controller

Application-optimized, high-performance controller IP for PCIe The Cadence® Controller IP for PCIe® 3.1 is a solution created for mobile applications that provides the means for these ...

20
PCI Express (PCIe) 2.1 Controller

Application-optimized, high-performance controller IP for PCIe The Cadence® Controller IP for PCIe® 2.0 is a solution created for less demanding designs. It has the logic required ...

21
Configurable controllers for PCIe 2.0/1.0 supporting Endpoint, Root Complex, Switch Port, and Dual Mode applications

The complete silicon-proven Synopsys IP solution, consisting of configurable digital controllers, PHYs, Integrity and Data Encryption (IDE) Security Modules, IP Prototyping Kits and verification ...

22
Configurable controllers for PCIe 3.1 supporting Endpoint, Root Complex, Switch Port, and Dual Mode applications

The complete silicon-proven Synopsys IP solution, consisting of configurable digital controllers, PHYs, Integrity and Data Encryption (IDE) Security Modules, IP Prototyping Kits and verification ...

23
Configurable controllers for PCIe 4.0 supporting Endpoint, Root Complex, Switch Port, and Dual Mode applications

The complete silicon-proven Synopsys IP solution, consisting of configurable digital controllers, PHYs, Integrity and Data Encryption (IDE) Security Modules, IP Prototyping Kits and verification ...

24
Configurable controllers for PCIe 5.0 supporting Endpoint, Root Complex, Switch Port, and Dual Mode applications

The complete silicon-proven Synopsys IP solution, consisting of configurable digital controllers, PHYs, Integrity and Data Encryption (IDE) Security Modules, IP Prototyping Kits and verification ...

25
Configurable controllers for PCIe 6.0 supporting Endpoint, Root Complex, Switch Port, and Dual Mode applications

The complete silicon-proven Synopsys IP solution, consisting of configurable digital controllers, PHYs, Integrity and Data Encryption (IDE) Security Modules, IP Prototyping Kits and verification ...

26
Automotive-grade controllers for PCIe 2.0/1.0 supporting Endpoint, Root Complex, Switch Port, and Dual Mode applications

The complete silicon-proven Synopsys IP solution, consisting of configurable digital controllers, PHYs, Integrity and Data Encryption (IDE) Security Modules, IP Prototyping Kits and verification ...

27
Configurable controllers for PCIe 4.0 and CCIX supporting Dual Mode applications

The complete silicon-proven Synopsys IP solution, consisting of configurable digital controllers, PHYs, Integrity and Data Encryption (IDE) Security Modules, IP Prototyping Kits and verification ...

28
PCIe Gen3 to SRIO Gen3 Bridge (FPGA)

Mobiveil’s PCIe Gen3 to SRIO Gen3 Bridge is a high-performance FPGA-based protocol conversion IP that enables seamless communication between PCI Express (PCIe) and Serial RapidIO (SRIO) systems. ...

29
USB 2.0 Host Controller (EHCI)

VHDL / Verilog source code provided ; USB EHCI specification compliant ; 33 MHZ PCI 2.1 compliant ; Supports low, full and high speed devices ; Technology independent ; Integrated root hub with ...

30
PCIe 3.0/3.1/USB3.0/SATA3 Combo PHY

The Innosilicon PCIE3.0 PHY is a highly programmable module that processes high-speed serial data to parallel data compatible with the PHY Interface for PCIE3.0 Super-Speed standard from Intel. ...

31
64G/56G SerDes

The Innosilicon 64G/56G SERDES PHY is a highly configurable PHY capable of supporting speeds up to 56Gbps within a single lane. For this datasheet, the PHY has been configured to support 64G/56G ...

32
32G Multi-SerDes PHY

The Innosilicon 32G SERDES PHY is a highly configurable PHY capable of supporting speeds up to 32Gbps within a single lane. For this particular datasheet, the PHY has been configured to support ...

33
25G Multi-SerDes PHY

The Innosilicon 25G SERDES PHY is a highly configurable PHY capable of supporting speeds up to 25Gbps within a single lane. For this particular datasheet, the PHY has been configured to support ...

34
12.5G Multi-SerDes PHY

The Innosilicon 12.5G SERDES PHY is a highly configurable PHY capable of supporting speeds up to 12.5Gbps within a single lane. For this particular datasheet, the PHY has been configured to ...

35
10G Multi-SerDes PHY

The Innosilicon 10G SERDES PHY is a highly configurable PHY capable of supporting speeds up to 10Gbps within a single lane. The PHY can be configured to support a wide range of HS SERDES protocols ...

36
32G Multi-SerDes For PCIe5.0/USB3.x PHY

The Innosilicon 32G SERDES PHY is a highly configurable PHY capable of supporting speeds up to 32Gbps within a single lane. For this datasheet, the PHY has been configured to support PCIe5.0/USB3.x ...

37
5G Multi-SerDes For PCIe2.0/USB3.0 PHY

The Innosilicon 5Gbps SERDES PHY is a highly configurable PHY capable of supporting speeds up to 5Gbps within a single lane. For this datasheet, the PHY has been configured to support PCIe2.0/USB3.x ...

38
8G Multi-SerDes For PCIe3.0/USB3.0 PHY

The Innosilicon 8Gbps SERDES PHY is a highly configurable PHY capable of supporting speeds up to 8Gbps within a single lane. For this datasheet, the PHY has been configured to support PCIe3.0/USB3.x ...

39
PCIe2.0 PHY & Controller

The Innosilicon SERDES PHY is a highly configurable PHY capable of supporting speeds up to 25Gbps within a single lane. For this particular datasheet, the PHY has been configured to support ...

40

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