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Pci pci express IP Listing

375 IP Cores (1 - 40)

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Compute Express Link (CXL) 3.1 Controller

The Rambus Compute Express Link® (CXL®) 3.1 controller is a parameterizable design for ASIC and FPGA implementations. It leverages the Rambus PCIe® 6.1 controller architecture for the CXL.io ...

1
Compute Express Link (CXL) 2.0 Controller

Rambus Compute Express Link (CXL) 2.0 Controller leverages a silicon-proven PCIe 5.0 controller architecture for the CXL.io path, and adds CXL.cache and CXL.mem paths specific to the CXL standard. ...

2
Compute Express Link (CXL) 2.0 Controller with AMBA AXI interface

Rambus CXL 2.0 Controller with AXI is a parameterizable Compute Express Link (CXL) controller Soft IP designed for ASIC and FPGA implementation. Rambus CXL 2.0 Controller with AXI leverages ...

3
PCIe 7.0 PHY IP supporting the latest features of the evolving PCIe 7.0 specification to enable 128 GT/s and up to x16 lane configurations

The multi-channel Synopsys PHY IP for PCI Express® (PCIe®) 7.0 meets today’s demands for higher bandwidth and power efficiency across backplane, and chip-to-chip channels. The PHY’s unique ...

4
PCIe 6.1 Controller

The Rambus PCI Express® (PCIe®) 6.1 Controller is a configurable and scalable design for ASIC implementations. It is backward compatible to the PCIe 5.0, 4.0 and 3.1/3.0, as well as version ...

5
PCIe 7.0 Controller

The Rambus PCI Express® (PCIe®) 7.0 Controller is a configurable and scalable design for ASIC implementations. It is backward compatible to the PCIe 6.0 and 5.0, as well as version 6.2.1 PHY ...

6
PCIe 7.0 Controller with AXI

The Rambus PCI Express® (PCIe®) 7.0 Controller with AXI is a configurable and scalable design for ASIC implementations. It is backward compatible to PCIe 6.2 and 5.0, and compatible with version ...

7
PCIe 7.0 Retimer Controller

The Rambus PCI Express® (PCIe®) 7.0 Retimer Controller provides a complete digital data path solution that delivers best-in-class latency, power and area, and accelerates the time-to-market ...

8
PCIe 7.0 Switch

The Rambus PCI Express® (PCIe®) 7.0 Switch is a customizable, multiport embedded switch for PCIe designed for ASIC and FPGA implementations. It enables the connection of one upstream port ...

9
PCIe 5.0 Serdes PHY IP, Silicon Proven in TSMC 12FFC

This Peripheral Component Interconnect Express (PCIe) x4 PHY is compliant with PCIe 5.0 Base Specification with support of PIPE 5.1 interface spec. Lower power consumption is achieved due to ...

10
PCIe 5.0 Controller supporting Endpoint, Root Port, Switch, Bridge and advanced features

Rambus PCIe 5.0 Controller is a configurable and scalable PCIe controller Soft IP designed for ASIC and FPGA implementation. Rambus PCIe 5.0 Controller is compliant with the PCI Express 5.0 ...

2 Testimonials
Serge Leef, Microsystems Technology Office Program Manager, DARPA

11
PCIe 5.0 Controller with AMBA AXI interface

Rambus PCIe 5.0 Controller is a configurable and scalable PCIe controller Soft IP designed for ASIC and FPGA implementation. Rambus PCIe 5.0 Controller is compliant with the PCI Express 5.0 ...

1 Testimonial
Russel Lindsay, Sr. Product Manager, Anritsu Corporation

12
PCIe 4.0 Controller supporting Endpoint, Root Port, Switch, Bridge and advanced features

Rambus PCIe 4.0 Controller is a configurable and scalable PCIe controller Soft IP designed for ASIC and FPGA implementation. The Rambus PCIe 4.0 Controller is compliant with the PCI Express ...

13
PCIe 4.0 Controller with AMBA AXI interface

Rambus PCIe 4.0 Controller is a configurable and scalable PCIe controller Soft IP designed for ASIC and FPGA implementation. The Rambus PCIe 4.0 Controller is compliant with the PCI Express ...

14
PCIe Gen3 to SRIO Gen3 Bridge (FPGA)

Mobiveil’s PCIe Gen3 to SRIO Gen3 Bridge is a high-performance FPGA-based protocol conversion IP that enables seamless communication between PCI Express (PCIe) and Serial RapidIO (SRIO) systems. ...

15
PCIe 5.0 Customizable Embedded Multi-port Switch

Rambus PCIe 5.0 Multi-port Switch is a customizable, Embedded PCIe Switch designed for ASIC and FPGA implementations enabling the connection of one upstream port and multiple downstream ports ...

16
PCIe Controller Testbench

PCIe Testbench from Rambus emulates a Root Complex device enabling simulation of a PCI Express design. This includes the following features: • Root Complex master requests are generated ...

17
PCIe Switch for USB4 Hubs, Hosts and Devices

Rambus PCIe Multi-port Switch for USB4 is a customizable, embedded Switch for PCI Express (PCIe) designed for implementations in USB4 devices. A fully configurable fanout switch, it provides ...

18
PCIe 6.2 Switch

The Rambus PCI Express® (PCIe®) 6.2 Switch is a customizable, multiport embedded switch for PCIe designed for ASIC implementations. It enables the connection of one upstream port and multiple ...

19
Compute Express Link (CXL) 1.1/2.0/3.0 Controller

The KappaCORE-64 from Alphawave Semi is a CXL™ Controller IP that implements the latest CXL 3.0 spec, which is backward compatible with CXL 2.0 and CXL 1.1 specs. This controller forms a complete ...

20
PCIe 5.0 Integrity and Data Encryption Security Module

PCI Express is a ubiquitous interface for a wide variety of applications, from connecting accelerators and peripheral devices to data center servers to their use in consumer electronics. PCI ...

21
PCIe 6.0 Integrity and Data Encryption Security Module

PCI Express is a ubiquitous interface for a wide variety of applications, from connecting accelerators and peripheral devices to data center servers to their use in consumer electronics. PCI ...

22
PCIe 6.0 PHY in TSMC (N6, N5, N4P, N3P, N3E)

The multi-channel Synopsys PHY IP for PCI Express® (PCIe®) 6.0 meets today’s demands for higher bandwidth and power efficiency across network interface card (NIC), backplane, and chip-to-chip ...

23
PCIe 6.0 PHY in Samsung (SF5A, SF4X, SF2)

The multi-channel Synopsys PHY IP for PCI Express® (PCIe®) 6.0 meets today’s demands for higher bandwidth and power efficiency across network interface card (NIC), backplane, and chip-to-chip ...

24
PCIe 7.0 PHY in TSMC (N5, N3P, N2P)

The multi-channel Synopsys PHY IP for PCI Express® (PCIe®) 7.0 meets today’s demands for higher bandwidth and power efficiency across backplane, and chip-to-chip channels. The PHY’s unique ...

25
High Performance NVMe for PCIe-based storage

Typical storage controllers are composed of a communication interface and a Nandflash controller. In this case, all the data flow is managed by the external host processor. However, this architecture ...

IPM-NVMe eval

26
create easily your own PCIe NVMe SSD

This architecture proposal is based on NVMe and NAND Flash Controller offloaded IPs. It is integrated in a FPGA and could be also be integrated in ASIC, allowing to provide design flexibility ...

IPM-NVMe eval

27
PCIe Gen5 NVMe SSD RAMDISK Reference Platform

Mobiveil’s RAMDISK-Gen5is a PCIe Gen5 and 1.4 NVMe compliant Ramdisk that emulates the next generation NVMe Gen5 SSDs with high performance. With high performance hardware based on Xilinx’s ...

28
IP Prototyping Kits for USB, DDR, MIPI, PCI Express protocols

The Synopsys IP Prototyping Kits, part of the IP Accelerated initiative, center around a complete, out-of-the-box reference design that consists of a validated IP configuration and necessary ...

29
PCI Express (PCIe) 5.0 Controller

Application-optimized, high-performance controller IP for PCIe The Cadence® Controller IP for PCIe 5.0 provides the logic required to integrate a root complex (RC), endpoint (EP), or ...

30
PCI Express (PCIe) 4.0 Controller

Application-optimized, high-performance controller IP for PCIe The Cadence® Controller IP for PCIe 4.0 provides the logic required to integrate a root complex (RC), endpoint (EP), or ...

31
PCI Express (PCIe) 3.1 Controller

Application-optimized, high-performance controller IP for PCIe The Cadence® Controller IP for PCIe® 3.1 is a solution created for mobile applications that provides the means for these ...

32
PCI Express (PCIe) 2.1 Controller

Application-optimized, high-performance controller IP for PCIe The Cadence® Controller IP for PCIe® 2.0 is a solution created for less demanding designs. It has the logic required ...

33
PCI Express PHY serial link PIPE Transceiver IP cell/hard macro

SMS5000 is a fully integrated CMOS transceiver that handles the full Physical Layer PCI Express protocol and signaling. It contains all necessary AFE (Analog Front End), Clock synthesis, Clock ...

34
PCI Express GEN-3/Display Port SERDES PHY - Samsung 28 28LPP

Analog Bits Programmable SERDES provides a Physical Media Attachment (PMA) Layer capable of signaling at multiple data rates and supports multi-protocol market needs including a wide range of ...

35
PCI Express GEN-3/SATA3 SERDES PHY - Samsung 28 28FDSOI

Analog Bits Programmable SERDES provides a Physical Media Attachment (PMA) Layer capable of signaling at multiple data rates and supports multi-protocol market needs including a wide range of ...

36
PCI Express GEN 3/4 Port SERDES PHY - Samsung 14LPP

Analog Bits Programmable SERDES provides a Physical Media Attachment (PMA) Layer capable of signaling at multiple data rates and supports multi-protocol market needs including a wide range of ...

37
Low Power PCIe2/SATA3SERDES PHY - TSMC 28HPC

Analog Bits Programmable SERDES provides a Physical Media Attachment (PMA) Layer capable of signaling at multiple data rates and supports multi-protocol market needs including a wide range of ...

38
Low Power PCIe3 SERDES PHY - TSMC 40G

Analog Bits Programmable SERDES provides a Physical Media Attachment (PMA) Layer capable of signaling at multiple data rates and supports multi-protocol market needs including a wide range of ...

39
Low Power PCIe3/SATA3SERDES PHY - TSMC 28HPC+

Analog Bits Programmable SERDES provides a Physical Media Attachment (PMA) Layer capable of signaling at multiple data rates and supports multi-protocol market needs including a wide range of ...

40

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