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Power-on-reset IP Listing

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Combined Power-On-Reset and Brown-Out-Reset in TSMC 22ULL

Combined Power-On-Reset and Brown-Out-Reset in TSMC 22ULL

1
Combined Power-On-Reset and Brown-Out-Reset in TSMC 40 ULP

Combined Power-On-Reset and Brown-Out-Reset in TSMC 40ULP process

2
Power-On-Reset GlobalFoundries

The agilePOR GP is a power-on-reset circuit. Based on a traditional architecture, it allows for programmable thresholds for normal and low power modes, programmable delays and includes hysteresis ...

3
Power-On-Reset Samsung

The agilePOR GP is a power-on-reset circuit. Based on a traditional architecture, it allows for programmable thresholds for normal and low power modes, programmable delays and includes hysteresis ...

4
Power-On-Reset SMIC

The agilePOR GP is a power-on-reset circuit. Based on a traditional architecture, it allows for programmable thresholds for normal and low power modes, programmable delays and includes hysteresis ...

5
Power-On-Reset UMC

The agilePOR GP is a power-on-reset circuit. Based on a traditional architecture, it allows for programmable thresholds for normal and low power modes, programmable delays and includes hysteresis ...

6
Power-On-Reset TSMC

The agilePOR GP is a power-on-reset circuit. Based on a traditional architecture, it allows for programmable thresholds for normal and low power modes, programmable delays and includes hysteresis ...

7
Power-On-Reset Intel

The agilePOR GP is a power-on-reset circuit. Based on a traditional architecture, it allows for programmable thresholds for normal and low power modes, programmable delays and includes hysteresis ...

8
SMIC 0.15um LV Power-On-Reset

Power-On-Reset circuit uses the RC delay to generate the system reset pulses.

9
SMIC 0.15um LV Power-On-Reset

Power-On-Reset circuit uses the RC delay to generate the system reset pulses

10
SMIC 0.18um Power-On-Reset

Power-On-Reset circuit uses the RC delay to generate the system reset pulses.

11
SMIC 0.18um Power-On-Reset

Power-On-Reset circuit uses the RC delay to generate the system reset pulses.

12
Power-On-Reset IP

Innosilicon Power-On-Reset (POR) IP provides reliable reset function for general applications. It is powered by analog supply and monitors digital supply. It generates POR_OUT signal to reset ...

13
Combined Power-On-Reset and Low-voltage detection in Samsung Foundries 65nm LFR6LP

Combined Power-On-Reset and Low-voltage detector designed in Samsung Foundries 65nm LFR6LP Bias current reference are provided by capacitor-less low quiescent LDO designed in the same process ...

14
Low-power Power-On-reset design in Samsung Foundries 65nm LFR6LP process

The POR-[1.8-5.5]-[0.9-1.4].01 is a Power-On-Reset designed in Samsung Foundries 65nm LFR6LP process nodes. It is used to monitor AVD and VDD supplies and to generate information to the SoC ...

15
Combined Power-On-Reset and Brown-Out-Reset in SMIC 40EF

Combined Power-On-Reset and Brown-Out-Reset in SMIC 40EF

16
Combined Power-On-Reset and Brown-Out-Reset in TSMC 22ULL

Combined Power-On-Reset and Brown-Out-Reset in TSMC 22ULL

17
Power-On-Reset and Brown-Out-Reset in TSMC 22ULL

Power-On-Reset and Brown-Out-Reset in TSMC 22ULL

18
Combined Power-On-Reset and Brown-Out-Reset in TSMC 22ULL

Combined Power-On-Reset and Brown-Out-Reset with reset signal filtering in TSMC 22ULL

19
1.8V RTC Power-On-Reset, UMC 28nm HPC Process

1.8V RTC Power-On-Reset, UMC 28nm HPC Process

20
SMIC 0.18um Power-On Reset

This is a Power-On-Reset circuit that generates a reset pulse when power supply is on. After the power V18 reaches a specific level, i.e., VTR, it will output a logic reset signal with pulse ...

21
SMIC 0.18um Low Leakage Power_On Reset

This is a Power-On-Reset circuit that generates a reset pulse when power supply is on. After the power AVDD18 reaches a specific level, VTR, it will output a logic reset signal with pulse width ...

22
GSMC 0.18um Power-On Reset

This is a Power-On-Reset circuit that generates a reset pulse when power supply is on. After the power V18 reaches a specific level, i.e., VTR, it will output a logic reset signal with pulse ...

23
SMIC 0.13um 3.3V/1.2V Power on Reset

The present Power-On-Reset circuit generates system reset pulses (RST) when both the 3.3V and 1.2V power suppliers are turned on. Output signal RST12 and RST33 will equal to AVDD and AVDDH respectively ...

24
IBM 65nm LPE 3.3V

The present Power-On-Reset circuit generates system reset pulses (RST) when the 3.3V power supplier is turned on. The output signal RST33 is positive reset and RSTN33 is negative reset. No external ...

25
IBM 65nm LPE 2.5V/1.2V

The present Power-On-Reset circuit generates system reset pulses (RST) when both the 2.5V and 1.2V power suppliers are turned on. Output signal RST12 and RST25 will equal to V12 and V25 respectively ...

26
SMIC 0.18um 1.8V Power on Reset

The present Power-On-Reset circuit generates System Reset Pulses (RST) when the 1.8V power supply is turned on. The output signal RST18 is of positive reset and RSTN18 is of negative reset. ...

27
IBM 65nm LPE 3.3V/1.2V Power On Reset

The present Power-On-Reset circuit generates system reset pulses (RST) when both the 3.3V and 1.2V power suppliers are turned on. The output signals RST12 and RST33 will equal to V12 and V33 ...

28
IBM 65nm SF 3.3V Power on Reset

The present Power-On-Reset circuit generates system reset pulses (RST) when the 3.3V power supplier is turned on. The output signal RST33 is positive reset and RSTN33 is negative reset. No external ...

29
IBM 65nm SF 3.3V/1.0V Power on Reset

The present Power-On-Reset circuit generates system reset pulses (RST) when both the 3.3V and 1.0V power suppliers are turned on. The output signal RST1P0 and RST33 will equal to V1P0 and V33 ...

30
GSMC 0.13μm Low Power Process VCC Detector

This IP contains two Voltage Detector (VDT) circuits and a Power-On-Reset (POR) circuit. The voltage detectors monitor the supply voltage of Bus Supplies VDDQIN and VDDNIN, and the Power-On-Reset ...

31
GSMC 0.13um Low Power e-Flash 1.5V POR

This IP is a Power-On-Reset circuit, it detects the voltage level of POR_VDDC port, when VPOR_VDDC rises higher than the threshold VPOR, POR outputs a high level; when VPOR_VDDC falls lower ...

32
GSMC 0.18um 3.3V Power on Reset

The present Power-On-Reset circuit generates system reset pulses (RST) when the power supplier is from 1.62V to 3.6V. The output signal RST is positive reset signal.

33
GLOBALFOUNDRIES 40nm LP 2.5V/1.1V Power on Reset

The present Power-On-Reset circuit generates system reset pulses (RST) when both the 2.5V and 1.1V power suppliers are turned on. Output signal RST11 and RST25 will equal to V11 and V25 respectively ...

34
Power on Reset

065TSMC_PoR_02 is a Power-on-Reset (PoR) circuit provides a reset signal to the chip when supply voltage reach required level. The block generates reset signal depending of the level supply ...

35
Advanced Power Controller w/ POR & BOR for PMU DC-DC and LDO ( Vin = 2.3-3.6V ) - TSMC 65nm

The SGC21412 is an Advanced Power Controller for integration in SoC. SGC APC is based on a configurable core that is configured for each specific SoC, delivering all the necessary auxiliary ...

36
Ultra Low Power PMU - Ultra Low Voltage (Vin > 1.2V), Ultra Low Power (6µW) LFoundry 0.15 μm

This macro-cell is an ultra low consumption Power Management Unit (PMU) core designed for LFoundry 0.15µm LF150 CMOS technology STD (Standard) and LP (Low Power) process. The circuit has 2 ...

37
Dual RSDS Transmitter, 24/18-bit color, 40-300Mb/s (SVGA/UXGA/full HDTV) LCD & Plasma display

This RSDS Transmitter interface IP is based on RSDS “Intra-Panel” Interface Specification rev1.0, dated May 2003 that allow the transfer of digital display data between a Timing Control ...

38
Dual RSDS Transmitter, 30-bit color, 40-300Mb/s (SVGA/UXGA/full HDTV) LCD & Plasma display

This RSDS Transmitter interface IP is based on RSDS “Intra-Panel” Interface Specification rev1.0, dated May 2003 that allow the transfer of digital display data between a Timing Control ...

39
Dual RSDS Transmitter, 30-bit color, 80-400Mb/s (SVGA/Full HDTV@120Hz)

This RSDS Transmitter interface IP is based on RSDS “Intra-Panel” Interface Specification rev1.0, dated May 2003 that allow the transfer of digital display data between a Timing Control ...

40

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