Simulation VIP for MIPI SPMI

Cadence provides a mature and comprehensive Verification IP (VIP) for the MIPI^® SPMI^sm (System Power Management Interface) protocol. Incorporating the latest protocol updates, the Cadence^® Verification IP for SPMI provides a complete bus functional model (BFM), integrated automatic protocol checks, and coverage model. Designed for easy integration in testbenches at IP, system-on-chip (SoC), and system levels, the VIP for SPMI helps you reduce time to test, accelerate verification closure, and ensure end-product quality. The VIP runs on all major simulators and supports SystemVerilog language along with associated methodologies, including the Universal Verification Methodology (UVM) and Open Verification Methodology (OVM).

Supported Specification: MIPI specifications for SPMI v1.0 and v2.0.

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