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1-56/112G Multi-protocol Serdes (Interlaken, JESD204, CPRI, Ethernet, OIF/CEI)
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VC Verification IP for CPRI
Synopsys® VC Verification IP for CPRI provides a comprehensive set of protocol, methodology, verification, and productivity features, enabling users to achieve accelerated verification closure of CPRI based designs.
Synopsys VC VIP, based on its next generation architecture and implemented in native System Verilog/UVM, runs natively on all major simulators. VIP can be integrated, configured, and customized with minimal effort. Test bench development is accelerated with built-in verification plan and functional coverage.
Synopsys VC VIP, based on its next generation architecture and implemented in native System Verilog/UVM, runs natively on all major simulators. VIP can be integrated, configured, and customized with minimal effort. Test bench development is accelerated with built-in verification plan and functional coverage.
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Block Diagram of the VC Verification IP for CPRI Verification IP
