Verification IP AXI4-LITE

UST Global VIP for AXI4-Lite (version: ARM IHI 0022D - ID102711) provides a comprehensive set of verification, methodology and protocol features, thus enabling designers to achieve a faster convergence & closure of AXI designs. AXI4-Lite VIP is implemented in System Verilog and UVM and is capable of running on all standard simulators. The VIP can be configured, integrated with minimal effort, at the same time, providing a lot of customization.

• see the entire Verification IP AXI4-LITE datasheet
• get in contact with Verification IP AXI4-LITE Supplier