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IP / SOC Products Articles

• Dual Mode C-PHY/D-PHY: Enabling Next Generation of VR Displays (May. 28, 2019)
  For many years, Virtual Reality (VR) and Augmented Reality (AR) were strongly linked to gaming and entertainment applications. Today, the VR/AR and their combined version, Mixed Reality (MR), have their applications extended to other domains like healthcare, military, education, manufacturing, retail, marketing and advertising. What are the challenges for next generation VR displays? What makes the MIPI interfaces the best fit for VR/AR/MR applications?
  
  
• Enabling Composable Platforms with On-Chip PCIe Switching, PCIe-over-Cable (May. 28, 2019)
  A number of interconnect protocols have emerged (NVMe-oF, CCIX, Gen-Z, CXL) promising to address the challenges introduced by the composability model. While these interconnect technologies mature and make their way towards mainstream adoption, system vendors still have various options that leverage the well established PCI Express protocol to enable scale-up and scale-out composable fabrics.
  
  
• Distorted Waveform Phenomena in 7nm Technology Node and its Impact on Signoff Timing Analysis (May. 06, 2019)
  In today’s deep sub-micron technology nodes like 16nm, 7nm & beyond, there is a huge challenge for accurate static timing calculation. Ever increasing routing congestion, thin metal layers and moreover very high speed signal propagation make these nodes prone to significant crosstalk effects.
  
  
• Image Processing - RTL Implementation of Median Filtering for Image Denoising (Apr. 25, 2019)
  This article explains step by step implementation of Median Filtering Algorithm in Verilog. This filtering technique is then applied to noisy image for denoising. This article also explains simple Verilog based testbench and Matlab scripts for image pre/post processing operation for verifying the same.
  
  
• Integrated ADAS Domain Controller SoCs with ISO 26262 Certified IP (Apr. 22, 2019)
  This article highlights the new integrated automotive ADAS domain controller SoC architecture, and describes how designers can accelerate their SoC-level certification and time-to-production with automotive-certified IP.
  
  
• Memory Testing - An Insight into Algorithms and Self Repair Mechanism (Apr. 08, 2019)
  Conventional DFT methods do not provide a complete solution to the requirement of testing memory faults and its self-repair capabilities. A promising solution to this dilemma is Memory BIST (Built-in Self-test) which adds test and repair circuitry to the memory itself and provides an acceptable yield. This article seeks to educate the readers on the MBIST architecture, various memory fault models, their testing through algorithms, and memory self-repair mechanism.
  
  
• Signoff Iteration Reduction Technique for Fixing Top Level Antenna (Apr. 01, 2019)
  While developing large-sized chips, “divide & conquer” techniques are used. This involves partitioning the design, implementing each block individually, and stitching them together at the top level. Even if the blocks are all clean with respect to physical and timing signoff, they show incremental violations when they are stitched together.
  
  
• A Heuristic Approach to Fix Design Rule Check (DRC) Violations in ASIC Designs @7nm FinFET Technology (Mar. 25, 2019)
  The intent of this paper is to explain the varied kinds of DRCs (Design Rule Checks) that are encountered in the Physical Design flow. This paper will discuss the Metal DRC violations (7nm Technology) generally seen at the block level and outline the practical approach to fix them.
  
  
• Guide to Choosing the Best DC-to-DC Converter for Your Application (Mar. 25, 2019)
  This white paper introduces a procedure for choosing the proper DC-DC switching converter for a given application. It explains basic, performance, and optional metrics in detail. It also demonstrates other practical aspects that are sometimes overlooked by system designers. Multiple application examples are provided.
  
  
• Which DDR SDRAM Memory to Use and When (Mar. 18, 2019)
  This whitepaper provides an overview of the JEDEC memory standards to help SoC designers select the right memory solution, including IP, that best fits their application requirements.
  
  
• Integration of power:communication interfaces in smart true wireless headset designs (Mar. 13, 2019)
  True Wireless Headsets (TWS headsets) attract attention thanks to better battery life, features, design and price points, but to be smart and user friendly, these devices require efficient data exchange between the charger cradle and earbuds.
  
  
• Reducing DFT Footprints: A Case in Consumer SoC (Mar. 11, 2019)
  Nowadays, placing multiple IPs on a single chip plays the most vital role in satisfying System on Chip ASIC specification requirements. Most of the time, these different IPs will have different clock domains.
  
  
• Hidden Signals: The Memories and Interfaces Enabling IoT, 5G, and AI (Mar. 11, 2019)
  This IDC Technology Spotlight Report, sponsored by Rambus, highlights key, often hidden, memory and interface technologies that are enabling high performance electronic systems to serve the disruptive trends of the next decade like IoT, 5G, and Artificial Intelligence.
  
  
• SOC Stability in a Small Package (Mar. 11, 2019)
  There are some IPs in SOC which are of general use and malfunction on them impacts a entire SOC. We Identified these IPs and analyze impact on SOC due to their malfunction.
  
  
• PCIe 5.0 vs. Emerging Protocol Standards - Will PCIe 5.0 Become Ubiquitous in Tomorrow's SoCs? (Mar. 04, 2019)
  Over the last 3 years, a number of protocol standards have emerged, aiming to address the growing demand for higher data throughput and more efficient data movement. While CCIX, Gen-Z, and OpenCAPI are relative newcomers, PCIe has been around for almost 2 decades. With the imminent release of version 5.0 of the PCIe Specification, SoC designers have a variety of options for supporting bandwidths in excess of 400 Gbit/s while improving overall communication efficiency.
  
  
• Right-Sizing Your Cryptographic Processing Solution (Mar. 04, 2019)
  In this white paper we investigate different cryptography implementation options and trade-offs, describe the measurable parameters, and analyze examples. We introduce and use the new EEMBC SecureMark™ benchmark for these measurements
  
  
• Guide to Choosing the Best LDO for Your Application (Feb. 18, 2019)
  To know which LDO you need, you must first define the application of your LDO and then examine which parameters are most important when dealing with that application. With the multiple parameters that characterize a particular LDO, it is not easy to determine which LDO is best suited. To help you figure this out, we have put together this reference. This guide presents a list of all the key LDO parameters along with their definitions, the most common applications of LDOs, and which parameters are critical for each.
  
  
• Creating a custom processor with RISC-V (Feb. 18, 2019)
  The RISC-V instruction set architecture is an open framework that allows design of a customized processor that can leverage tools and software libraries created for the standard versions.
  
  
• Transitioning from DDR4 to DDR5 DIMM Buffer Chipsets (Feb. 07, 2019)
  There are a number of key changes to DDR that introduce new design challenges. However, savvy designers will use the transition time to nail down solutions.
  
  
• What can GPUs bring to ADAS? (Feb. 07, 2019)
  One of the most talked about topics in the automotive industry today is advanced driver assistance systems (ADAS). These systems assist the driver in dealing with potential issues in a number of ways.
  
  
• Achieving Groundbreaking Performance with a Digital PLL (Feb. 04, 2019)
  This article compares analog, first-generation digital, and second-generation digital PLLs. It evaluates which type of PLL may be best in which situation. It further discloses a roadmap into other application areas, including general purpose / logic clocking, and regular low-jitter PLLs.
  
  
• The Four Characteristics of an Optimal Inferencing Engine (Jan. 31, 2019)
  Advice on how to compare inferencing alternatives and the characteristics of an optimal inferencing engine.
  
  
• The Tradeoffs of Low Dropout (LDO) Voltage Regulator Architectures and the Advantages of "Capless" LDOs (Jan. 28, 2019)
  Power management of battery-powered electronic devices is becoming increasingly more important for the microelectronics industry. This white paper details the difference between low dropout (LDO) voltage regulators that use external output capacitors and those that do not, and how your system designs can benefit from not using an output capacitor. Well-designed capless LDO voltage regulators can have multiple benefits, and they are presented here.
  
  
• Secure SOC for Security Aware Applications (Jan. 14, 2019)
  Security is a two-way sword, increasing the security makes user difficult to access the chip and increasing user access increases chances for the chip to be hacked.
  
  
• Bulletproofing PCIe-based SoCs with Advanced Reliability, Availability, Serviceability (RAS) Mechanisms (Dec. 19, 2018)
  We start this article by defining “RAS” in the context of PCIe interfacing and looking at the provisions for RAS mechanisms in the PCIe Specification. We then explore some potential PCIe hazards SoC designers can face and the RAS mechanisms that can be implemented to detect, recover, or prevent these hazards. We conclude with recommendations for choosing a PCIe silicon IP solution that helps mitigate these risks.
  
  
• Extending 8K over a single, cost-effective wire with TICO lightweight compression (Dec. 13, 2018)
  With HD omnipresent and 4K seemingly still in its early stages, an even higher resolution, namely 8K (or UHDTV2) is arising. Display and projection manufacturers are already presenting their first 8K-capable products and the 2018 Winter Olympics were partly filmed in this currently largest video resolution format. Taking a peek into the future, Japan’s national TV “NHK” has even announced to broadcast the full Olympic games on home turf in 2020 in glorious 8K.
  
  
• PCI Express 3.0 needs reliable timing design (Dec. 03, 2018)
  PCI Express (PCIe) is an important standard for chip-to-chip communications and serves as a standard for connecting motherboards to peripheral cards. It can be challenging, however, to implement the reference clock so that it meets the various requirements of the PCIe standard.
  
  
• Designing an Effective Traffic Management System Through Vehicle Classification and Counting Techniques (Nov. 29, 2018)
  This white paper proposes an effective approach for moving vehicle classification followed up by vehicle counting, for classified types of vehicles. This data helps in strategic city planning, and in generating meaningful insights for improving efficiency and reliability in Traffic Management.
  
  
• Improving reliability of non-volatile memory systems (Nov. 19, 2018)
  Complex systems like Advanced Driver-Assistance Systems (ADAS), medical, and industrial applications need to be reliable, secure, and safe. In these systems, firmware and associated data are stored in Non-Volatile Memory (NVM) because code and data must be retained when power is not being supplied. Thus, NVM plays a crucial role in system reliability.
  
  
• Gen-Z Primer for Early Adopters (Nov. 12, 2018)
  In this article we look at the Gen-Z fabric as a solution to eliminate existing system bottlenecks and significantly improve system efficiency and performance by unifying communication paths and simplifying software using the CPU-memory load/store language throughout.