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IP / SOC Products Articles

• Auto OEMs, Tier-Ones: Think SoC Designs (Oct. 09, 2018)
  Automotive OEMs and Tier-1 suppliers are in a unique situation these days. Game-changing technology undertakings and hyper business growth in advanced driver assistance systems (ADAS) and autonomous cars are turning automotive design platforms upside-down.
  
  
• New Power Management IP Solution Can Dramatically Increase SoC Energy Efficiency (Oct. 01, 2018)
  This Position Paper describes a family of Power Management IP solutions integrated by Dolphin Integration’s customers into their SoC to drastically improve Energy Efficiency (EE). SoC performance metric is changing, moving from pure performance metric (GHz or MIPS) to performance efficiency and minimum power consumption. This new metric, already crucial for IoT or mobile devices, is becoming key in various applications, like automotive, embedded or space.
  
  
• CPU Soft IP for FPGAs Delivers HDL Optimization and Supply Chain Integrity (Sep. 27, 2018)
  RISC-V open ISA can help military and aerospace designers who are facing challenges of minimizing power consumption, BOM cost and board area by allowing the optimization of the instruction set to give the most efficient implementation for each specific application.
  
  
• Optimizing AI and Machine Learning with eFPGAs (Aug. 31, 2018)
  Why the performance and flexibility offered by eFPGA is turning out to be a game changer for anyone designing AI and machine learning and struggling to meet the compute demands.
  
  
• Fundamentals of Semiconductor ISO 26262 Certification: People, Process and Product (Aug. 20, 2018)
  This paper explains the changes in the role of the semiconductor industry in the automotive supply chain and seeks to enhance the reader’s knowledge regarding all aspects of the ISO 26262 standard. This paper also discusses the standard’s applicability not only to electronic products, but also to the people and processes employed to create them.
  
  
• Why Isn't 56 Gbps Impossible? (Aug. 16, 2018)
  How fast can you force data through a pair of wires? It is a trick question, of course. The answer depends on the wires, the material and geometry around them, the distance, and your choice of transceiver technology.
  
  
• 4K Video over IP workflows (Jul. 16, 2018)
  Considering the necessary bandwidth for the next generation of television with UHDTV resolutions and higher frame rates, live uncompressed transport across 10GB Ethernet network or existing SDI infrastructure is not possible anymore. In fact, uncompressed 4K video at 60fps 4:2:2 requires 12Gbps or more for 4:4:4.
  
  
• Sharing NVMe SSDs for heterogeneous architectures (Jul. 09, 2018)
  New computing applications, such as big data analytics and deep learning, need very optimized and well balanced computing, networking and storage resources. After being developed on CPU-centric architectures, it is now going on heterogeneous architectures by using computing accelerators like FPGAs and GPUs.
  
  
• Convey UHD 4K Video over 1Gbit Ethernet with the intoPIX JPEG 2000 "Ultra Low Latency" compression profile (Jul. 02, 2018)
  Considering the uncompressed bandwidth of a UHD 4K video stream in 4:2:2 or 4:4:4 and the massive amount of deployed Gigabit Ethernet infrastructures, a codec that can offer the same benefits in terms of quality, latency and reliability as uncompressed transport, with a sufficient compression ratio to go under 1Gbit/second, is a key advantage.
  
  
• How embedded FPGAs fit AI applications (Jun. 18, 2018)
  Artificial intelligence, and machine learning in particular, is reshaping the way the world works, opening up countless opportunities in industry and commerce, but the optimum hardware architecture to support neural network evolution, diversity, training and inferencing is not determined. Alok Sanghavi surveys the landscape and makes the case for embedded FPGAs.
  
  
• NVMe host IP for computing accelerator (May. 29, 2018)
  NVM Express (NVMe) SSDs are well adopted by the storage industry. It delivers high performances in term of IOPS, throughput and latency. It comes with a various range of capacity and form factors including PCIe Add-In-Card, 2.5" U.2, M.2 and recently as a single BGA chip.
  
  
• Considerations Regarding Benchmarking eFPGAs (Embedded FPGAs) (May. 22, 2018)
  There are many things to consider, but if you choose the right solution for your particular application, you will be able to unlock the full potential of your eFPGA.
  
  
• Multi-Channel Multi-Rate (MCMR) Forward Error Correction (FEC) - IP for High Speed Networking Applications (May. 21, 2018)
  The need for higher and higher bandwidth is growing, which is pushing the SerDes speed to 56G and beyond. The next generation of networking devices are already pushing for 400G bandwidth and above. Both the OIF CEI-56G and IEEE working groups have ratified the 56G specifications, and for higher speed SerDes, PAM4 signaling is the way forward.
  
  
• Demystifying MIPI C-PHY / DPHY Subsystem (Apr. 26, 2018)
  The newest member of the MIPI® PHY family, the C-PHY, arrived in October 2014 to a mixture of excitement and apprehension. How would this new C-PHY compare to the MIPI D-PHY and M-PHY®? What would differentiate the C-PHY, and would it be compatible enough with the D-PHY so that both could coexist in a hybrid subsystem? Now, years later, the answers are clear.
  
  
• Packet-based fronthaul - a critical enabler of 5G (Apr. 23, 2018)
  This paper will outline the benefits of a packet-based fronthaul technology to the business case for 5G NR virtualized RANs, and describe Comcores’ demonstrator. This provides detailed measurements based on four important enablers of the new RAN architecture - 5G NR; 100 MHz channels; IEEE 1914.3 RoE encapsulation and mapping; and functional splits which offload some of the baseband processing to the radio unit in order to boost fronthaul efficiency still further. There is also a coexistence path with installed CPRI links, and the eCPRI roadmap.
  
  
• Low Voltage SRAM - The Missing Link (Apr. 18, 2018)
  Near threshold design is delivering improved battery life for demanding battery powered applications. One key challenge remains - what about the SRAM?
  
  
• How to create energy-efficient IIoT sensor nodes (Apr. 11, 2018)
  When you’re designing sensor node devices destined for the industrial internet of things (IIoT), chances are they need to be battery-powered. And given the number of these expected to be deployed, and their often-remote locations, changing or charging a battery frequently isn’t an option.
  
  
• Bluetooth Mesh - the Next Wave of IoT Technology (Apr. 09, 2018)
  The adoption of the Bluetooth low energy (Bluetooth LE) specifications v4.0/v4.2 standards is being driven by adoption in several markets such as the Health and Fitness devices, Beacons, Asset tracking, Home automation, PC Peripherals etc. Bluetooth low energy 5, together with the Bluetooth LE Mesh specifications are set to make Bluetooth the ‘Connectivity of Choice’ in IoT markets such as Connected Home, Commercial Lighting and Industrial Wireless Sensor Network markets.
  
  
• Afternoon diversion: Design your own microprocessor (Apr. 09, 2018)
  I used FPGAs a lot in my designs and usually needed a processor for some housekeeping or control purpose. Although FPGA-based processors were available, such as Altera’s Nios, they did use quite of lot of resources and often required external code memory, encumbered as they were by C compilers and even operating systems. I decided to design my own minimal microprocessor for those simple tasks such as I2C control of peripherals, or simple control interfaces such as digital encoders and character LCD displays.
  
  
• Killer Apps Driving Adoption of USB 3.1 Gen 2 (Apr. 02, 2018)
  Design-in of USB 3.1 Gen 2 has become much more common in semiconductor devices. This adoption is being driven by a broad range of applications, most involving large file sizes or high-resolution video streams, that demand high bandwidth. Neither earlier generations of USB nor other connectivity solutions such as wireless Ethernet or Bluetooth can meet these requirements. The 10 Gbit/second bandwidth of USB 3.1 Gen 2 satisfies all current needs, with room for future growth. This white paper discusses the alignment of applications and Gen 2, showing how alternatives fail to make the grade.
  
  
• From ADAS to Autonomous Cars: Key Design Lessons (Mar. 27, 2018)
  Autonomous driving can be challenging. But here are three major lessons that automotive developers have learned while streamlining the ADAS designs during the past few years.
  
  
• Types of Storages for Computing System-On-Chips (Mar. 05, 2018)
  We are living in an age where we generate the same amount of data each year that has been generated since antiquity. Ever wondered how and where these peta /exa/zetta bytes of data are stored?
  
  
• Three Design Aspects you shouldn't miss while building an NB-IoT Protocol Stack (Feb. 26, 2018)
  It is very important that the design aspects of the NB-IoT device protocol stack ensure low module cost and low energy consumption. This is required to match the industry expected module costs. This paper outlines some of the NB-IoT Protocol stack specification flexibilities and generic design aspects that are to be considered to meet the above requirements, especially with reference to LTE.
  
  
• A design of High Efficiency Combo-Type Architecture of MIPI D-PHY and C-PHY (Feb. 05, 2018)
  MIPI C-PHY is suitable for mobile camera and display applications. In this paper, we proposed an effective active C-PHY driver scheme without any increase of the size and control pins. Additionally, C-PHY has many characteristics in-common with D-PHY because many parts of C-PHY were adapted from D-PHY. Therefore, we present a combo-type architecture of MIPI D-PHY and C-PHY.
  
  
• Types of Memories in Computing System-On-Chips (Jan. 29, 2018)
  What types of memories are needed for a computing system? Let me try to answer this question with an analogy. Have you ever solved a complex math problem without a paper?
  
  
• The Ideal Solution for AI Applications - Speedcore eFPGA (Jan. 22, 2018)
  Artificial intelligence (AI) is reshaping the way the world works, opening up countless opportunities in commercial and industrial systems. These new architectures will perform functions such as load balancing and allocating resources such as wireless channels and network ports based on predictions learned from experience.
  
  
• Run by Chips, Secured with Chips - Hardware Security with NeoPUF solutions (Jan. 08, 2018)
  eMemory NeoPUF Entropy IP provides a quality PUF entropy up to 64K bits, and NeoPUF Key Manager IP offers a ready-to-use key generator to accelerate time-to-market. The solutions address key issues of existing technologies and can secure the hardware from the very beginning of chip manufacture.
  
  
• A Brief History of Process Node Evolution (Jan. 02, 2018)
  The semiconductor industry has produced improved Integrated circuits (ICs) year after year by reducing chip area and making ICs more power efficient. In addition to new circuit innovations, a major driver for these improvements has been the advancement of fabrication process or technology nodes that essentially make electronic devices smaller and more power optimized.
  
  
• Understanding Flash memory (Dec. 18, 2017)
  Flash memory is currently the most widely used type of non-volatile memory. NAND Flash is optimised for file storage, to replace traditional disk drives. This article provides an overview of how NAND Flash technology works, and the role of the controller to optimise the performance and lifetime of the Flash memory.
  
  
• Modular Design Of Level-2 Cache For Flexible IP Configuration (Dec. 11, 2017)
  This paper presents an innovative level 2 cache design that meets the requirements of flexibility, configurability, low power, and small area for embedded systems.