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IP / SOC Products Articles

• Dynamic Margining: The Minima Approach to Near-threshold Design (Nov. 30, 2017)
  Energy consumption has become the most important parameter for today’s batterypowered electronic devices. The need to reduce energy consumption has led the industry to reconsider the concept of near-threshold design. Legacy design, a static margining approach to power/performance trade-offs, will leave most of the potential energy savings on the table. New offerings in this arena include both integrated circuit (IC)-based and intellectual property (IP)-based solutions, where IP-based solutions offer a faster time-to-market among other benefits.
  
  
• IPs for automotive application - Functional Safety and Reliability (Nov. 27, 2017)
  An electronic design that can be used in multiple ASICs/SoCs is a potential “IP” in the semiconductor industry. The premise of semiconductor IP market is simple – IP vendor focuses on designing, maintaining and updating the IP and ASIC/SoC companies focus on their differentiation, thereby fuelling innovation and reducing time-to-market.
  
  
• The Secret to Building IP at the Cutting Edge (Nov. 20, 2017)
  At 7nm and beyond, the cost and time to develop IP is very high. To gain a suitable return, it's critical to have an efficient design methodology that produces a portfolio of attractive solutions in many process variants, metal stacks, Vt selections, and even completely different foundries.
  
  
• The Future of Microcontrollers (Nov. 20, 2017)
  Integration of eFPGA into microcontrollers is happening today now that this technology is available from multiple suppliers in 180nm to 16nm process nodes.
  
  
• Why is Analog increasingly important in the Digital Era? (Nov. 16, 2017)
  Since its invention in the `60s, integrated circuit development has seen an aggressive and cyclic pace for improvement pushed by specific disruptive applications. These once were military/aerospace, mainframe computer, minicomputer, personal computers, networking, mobile and more recently smartphones. The traditional approach has always been to make the most out of digital and support it, when needed, with analog submodules.
  
  
• Overcoming Timing Closure Issues in Wide Interface DDR, HBM and ONFI Subsystems (Nov. 13, 2017)
  In wide chip interfaces like DDR, HBM and ONFI, it can be challenging to synthesize and connect high-frequency controllers to the PHY hard macros. Clock trees can be expansive, pushing tools to their limits, and often multiple clock domains are needed.
  
  
• eFPGA IP Density, Portability & Scalability (Nov. 13, 2017)
  There are multiple eFPGA suppliers in the market today: Achronix, Adicsys, Efinix, Flex Logix™, Menta, QuickLogic. There are 3 different business models and engineering approaches to eFPGA which you should understand to assess how it will impact your success in using their eFPGA IP and their viability as a supplier long term.
  
  
• Rapid SoC Proof-Of-Concept For Zero Cost (Nov. 06, 2017)
  Your company provides analog/mixed-signal (AMS) and sensor-based ICs, but your best customer wants you to create a system on a chip (SoC) that includes a digital processor. With little experience with digital processors, you need to quickly provide a proof-of-concept to your customer that shows the viability of this new IC in the next few days. And, you have very little budget.
  
  
• The Battle of Data center Interconnect Fabric (Oct. 30, 2017)
  With the exponential increase in off-chip bandwidth requirement, chip-to-chip interconnect is turning out to be the bottleneck of the information highway. Such bottlenecks invariably drive a new wave of innovation. During 1990s and around the turn of the millennium, rapid adoption of personal computers and development of various IO devices fuelled early innovations in interconnect technology and interfaces such as SATA, SAS, USB, PCIe were defined.
  
  
• Combining USB Type-C and DisplayPort support in portable implementations (Oct. 09, 2017)
  Using USB Type-C connectors to combine both USB-C 3.1 and DisplayPort data streams, to support data, audio, video and power connections on a single port
  
  
• Power Management for Internet of Things (IoT) System on a Chip (SoC) Development (Sep. 18, 2017)
  There are many factors that must be considered when developing a custom System on a Chip (SoC) for Internet of Things (IoT) applications. Chief among these are the power management circuits on the die. Vidatronic offers this white paper to discuss these considerations and all of the various circuit blocks that can be found in this application. Vidatronic IP solutions are discussed and the benefits they bring to IoT SoC designers.
  
  
• Reduce Time to Market for FPGA-Based Communication and Datacenter Applications (Sep. 14, 2017)
  As FPGA-based realizations become bigger and more complex, synthesis tools that deliver an automated flow are the obvious choice for creating optimized designs in a timely manner.
  
  
• The case for integrating FPGA fabrics with CPU architectures (Aug. 28, 2017)
  Physics restricts how much further process geometry shrinkage can take us in terms of boosting processor throughput.
  
  
• Asynchronous reset synchronization and distribution - Special cases (Aug. 14, 2017)
  Lack of coordination between asynchronous resets and synchronous logic clocks leads to intermittent failures on power up. In this series of articles, we discuss the requirements and challenges of asynchronous reset and explore advanced solutions for ASIC vs FPGA designs.
  
  
• Asynchronous reset synchronization and distribution - ASICs and FPGAs (Aug. 07, 2017)
  
  
  
• Asynchronous reset synchronization and distribution - challenges and solutions (Jul. 30, 2017)
  Lack of coordination between asynchronous resets and synchronous logic clocks leads to intermittent failures on power up. In this series of articles, we discuss the requirements and challenges of asynchronous reset and explore advanced solutions for ASIC vs FPGA designs.
  
  
• Improving Battery-Powered Device Operation Time Thanks To Power Efficient Sleep Mode (Jul. 20, 2017)
  Allowing battery-powered devices to run, without battery recharge, for years rather than months, partakes in enhancing significantly end-user satisfaction and is a key point to enabling the emergence of IoT applications. Numerous applications, such as M2M, BLE, Zigbee…, have an activity rate (duty cycle) such that the power consumption in sleep mode dominates the overall current drawn by the SoC (System on Chip). For such applications, the design of the “Always-On power domain" (a.k.a AON power domain) is pivotal.
  
  
• Megatrends Drive 200mm Fab Renaissance (Jul. 17, 2017)
  The past year has seen a resurgent interest in 200mm fabrication. In this paper, I will discuss why this is and answer the question, "Can 200mm fabs have a profitable future?"
  
  
• Generating High Speed CSI2 Video by an FPGA (Jul. 17, 2017)
  In this article, we show how fast video streams conforming to MIPI CSI2 rev2.0 over MIPI DPHY rev1.2 can be generated, using VLSI Plus’ SVTPlus-CSI2-F IP core, with simple off-FPGA analog front-end. The high bit rates can be achieved with a relatively slow FPGA clock frequency, trading off FPGA resources for simple timing closure.
  
  
• How to Reduce FPGA Logic Cell Usage by >x5 for Floating-Point FFTs (Jul. 10, 2017)
  Here we provide rational for using Centar’s floating-point IP core for the new Altera Arria 10 and Stratix 10 FPGA platforms. After a short contextual discussion section, a comparison of various FFT designs follows based on compilations to a couple of FPGAs. Here it is shown that LUT/register usage can be drastically reduced with this new class of FPGAs. The following section summarizes why Centar’s architecture is so effective in taking advantage of the new DSP block hardware.
  
  
• Context Based Clock Gating Technique For Low Power Designs of IoT Applications - A DesignWare IP Case Study (Jul. 03, 2017)
  This paper discusses about the intelligent low power techniques such as context based clock gating and how they are useful for IoT applications. It also describes how it improves the overall power efficiency of the system. The power statistics shared shows how the overall idle power and functional power consumption is significantly reduced. Further we discuss about how it can be combined with few other low power techniques to reduce the overall power
  
  
• Addressing SRAM Verification Challenges (Jun. 26, 2017)
  Verification is an integral part of any integrated circuit development process. The verification process must establish that the design meets its specified yield and performance criteria over the full range of operating conditions before tape-out sign-off. The process generally involves taking abstractions of the design in appropriate forms, for example post-layout extracted netlists, and running simulations to validate the design performance. The verification process must address many different aspects of yield and performance, so several different types of design abstraction and simulation tooling may be required to complete the process. In the case of SRAM this is particularly true.
  
  
• Introduction to Low Dropout (LDO) Linear Voltage Regulators (Jun. 15, 2017)
  Linear voltage regulators are key components in any power-management system that requires a stable and ripple-free power supply. A subset of linear voltage regulators is a class of circuits known as low dropout (LDO) regulators. This paper explains the fundamentals of LDOs and introduces Vidatronic’s LDO technology which solves many of the known shortcomings of LDO circuits.
  
  
• Communication Processors March on But 5G Demands Much More (Jun. 12, 2017)
  Development is well underway on Gigabit LTE cellular communications systems that promise an order of magnitude increase in data transfer rates and 5G is close behind. Small cell access nodes will form an essential part of both systems but new communications processors are needed to make these a reality.
  
  
• Ultra HD H.264 Video Codec IP solution on Zynq FPGA (May. 22, 2017)
  Numerous industries in broadcast, cable, videoconferencing and consumer electronics space are using H.264 as the video codec of choice for their products and services. The H.264/AVC video coding standard achieves a significant improvement in coding efficiency with increased computational complexity relative to former standards.
  
  
• USB Type-C and power delivery 101 - Power delivery protocol (May. 15, 2017)
  As described in the first part of this two-part series, USB Type-C is the newly introduced and powerful interconnect standard for USB. When paired with the new Power Delivery (PD) specification, Type-C offers enhancements to the existing USB 3.1 interconnect that lower the cost and simplify the implementation of power delivery over USB. In this article, we describe the USB Type-C power delivery protocol.
  
  
• USB Type-C and power delivery 101 - Ports and connections (May. 08, 2017)
  In this two part series, we describe power delivery with USB Type-C, starting with ports and connectors in this article, followed by the power delivery protocol in part two.
  
  
• Improving Inter Integrated Circuits - From Sensor Hubs to Platform Management Solutions (May. 01, 2017)
  This paper attempts to redefine these existing system level solutions using I3C and examine the improvements it can bring over I2C based solutions. Furthermore, it presents a seamless and risk free migratory path to the industry from these I2C based architectures to I3C based architectures using proven Synopsys Solutions.
  
  
• Achieving High Performance Non-Volatile Memory Access Through "Execute-In-Place" Feature (Apr. 24, 2017)
  The paper discusses about Execute In Place(XiP) feature in embedded systems implemented through the SPI protocol. Concept of XiP are explained including how it improves the overall throughput and efficiency of a system. Results are shared on the overall system throughput improvement. Further we discuss about various methods by which user can make most out of this feature.
  
  
• Allowing server-class storage in embedded applications (Apr. 19, 2017)
  In this article, a new way to implement high performance data storage is presented, allowing the use of server-class storage technology in an embedded environment.