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IP / SOC Products Articles

• A 4-MHz parameterized Logarithm-Square Root IP-Core (Mar. 27, 2017)
  Abstract Logarithms and square root are non-elementary operations frequently used in digital signal processing. In this work, implementation and design of an IP-Core to compute square root and multibase logarithm is presented. The design is parameterized in fixed point notation achieving a low arithmetic error even when irrational numbers are being calculated. The module was synthesized in ASIC using FSC0G_D_GENERIC_CORE from UMC and in FPGA occupying 518 logic elements and two DSP blocks for multiplication.
  
  
• Can 10 Gbps Ethernet be an Embedded Design Solution? (Mar. 21, 2017)
  10 Gbps Ethernet (10GbE) has established itself as the standard way to connect server cards to the top-of-rack (ToR) switch in data-center racks. So what’s it doing in the architectural plans for next-generation embedded systems? It is a tale of two separate but connected worlds.
  
  
• Reusable Verification Model for Motion estimation Algorithm (Mar. 20, 2017)
  Increasing functionalities of application specific integrated circuits (ASIC) require rather more efficient verification methods. In this paper, a novel verification model (VM) for low complexity motion estimation (ME) hardware architecture used in a video encoder is proposed.
  
  
• An introduction to ARM Cortex-M0 DesignStart (Mar. 09, 2017)
  The availability of the ARM Cortex-M0 processor within ARM’s DesignStart portal makes designing and prototyping a Cortex-M0 based system-on-chip (SoC) much easier. Quick and free-of-charge access to one of the most licensed Cortex-M processors speeds up the development and validation of new, custom SoCs that will enable the growth of smart connected devices.
  
  
• Safety Verification and Optimization of Automotive Ethernet Using Dedicated SoC FIT Rates (Mar. 09, 2017)
  This article explains a new holistic methodology that combines analytic methodologies such as FMEDA with simulation-based methodologies to significantly reduce the safety verification effort and achieve faster product certification. Automated fault injection is a well-established test method used to verify the correct implementation of safety mechanisms and to get a much more realistic estimation of the FIT rates.
  
  
• Making Better Front-End Architectural Choices Avoids Back-End Timing Closure Issues (Mar. 01, 2017)
  Today’s SoC architectures are so complex that they are creating rifts between design teams in any given project. For example, when architects decide on the functionality and the underlying data flow of a design during the front-end of the chip design process, they often have little preconception of the myriad timing closure challenges that get handed to synthesis place and route teams during the back-end of the processes.
  
  
• Hybrid Hardware Architecture for Low Complexity Motion Estimation Algorithm (Feb. 13, 2017)
  Nowadays hybrid hardware architecture (HHA) becomes increasingly popular in embedded systems (ES). In this paper HHA is presented for low bit depth motion estimation (ME) algorithm. Intellectual property (IP) core is designed for ME algorithm by using field programmable gate array (FPGA) and this IP is integrated with processor system (PS) to investigate its performance in an ES. Designed ME based IP has data bus of size 32bits and is working properly up to 200 MHz. Experiments show that the HHA is integrated successfully and gives expected results in real time.
  
  
• Configurable Microprocessor for Life Essential Devices (Feb. 06, 2017)
  This paper will explore how processors have evolved with attributes such as configurability and extensibility to enable the next generation of electronics.
  
  
• A Review Paper on CMOS, SOI and FinFET Technology (Feb. 01, 2017)
  In 1958, the first integrated circuit flip-flop was built using two transistors at Texas Instruments. The chips of today contain more than 1 billion transistors. The memory that could once support an entire company’s accounting system is now what a teenager carries in his smartphone. This scale of growth has resulted from a continuous scaling of transistors and other improvements in the Silicon manufacturing process.
  
  
• Electronic Circuit Design for RF Energy Harvesting using 28nm FD-SOI Technology (Jan. 27, 2017)
  A design of voltage doubler circuit has been studied in context of electromagnetic energy harvesting using 28 nm FD-SOI technology. After analysis of the operating constraints of the circuit, the choice was made in favour of NLVT transistor configured as a diode. The design and optimization of the circuit is presented as well as the influence of the polarization of the substrate.
  
  
• A Cost-Effective Reuse Method of Off-the-Shelf MIMO Wireless LAN IPs with a Nested Spatial Mapping (Jan. 23, 2017)
  This paper presents a spatial mapping which turns dual data streams of MIMO system into an equivalent single stream. It is achieved by shrinking the constellation of the secondary stream into that of the primary data stream so that the primary one can be decoded even with a simple SISO de-mapper.
  
  
• Turning cars into mobile devices: MIPI (Jan. 17, 2017)
  Everyone remembers their first car – how you could go where you wanted to go, moving faster and going longer distances – you were mobile. Yes, our cars made us mobile, but today’s cars are becoming mobile devices themselves.
  
  
• Embedded FPGA: Changing the Way Chips Are Designed (Jan. 09, 2017)
  One of the most critical problems chip designers face today is having to reconfigure RTL at any point in the design process, even in-system. Unfortunately, chip designers have no way of knowing if they will have to do this until it is too late. Any changes at that point end up costing millions of dollars and delaying projects by months.
  
  
• Design Considerations for High Bandwidth Memory Controller (Jan. 09, 2017)
  High Bandwidth Memory (HBM) is a high-performance 3D-stacked DRAM. It is a technology which stacks up DRAM chips (memory die) vertically on a high speed logic layer which are connected by vertical interconnect technology called TSV (through silicon via) which reduces the connectivity impedance and thereby total power consumption.
  
  
• Latch-Based RAMs and the Hidden Capacitor (Jan. 04, 2017)
  Is there a place for a volatile DRAM replacement? While the VLT as a DRAM replacement might be attractive, any success hinges on effective and innovative solutions to some major problems.
  
  
• A Flexible 200kHz-20MHz Ring Oscillator in a 40nm CMOS Technology (Dec. 12, 2016)
  In this paper, we present a flexible ring oscillator IP designed for a 40nm CMOS technology, whose oscillation frequency can be chosen from 200kHz to 20MHz. It was developed using a new design approach, in which analog IPs are designed from scratch to be flexible, employing modular blocks that can be easily customized. The IP is silicon proven. It works with a supply voltage of 1.2V and features 5% frequency accuracy, occupying an area of 0.0022mm2.
  
  
• Best insurance for your design? System performance analysis (Dec. 05, 2016)
  It sounds trite, but it’s always true: The stakes are higher in system-on-chip (SoC) design than ever. And tomorrow they’ll be even higher.
  
  
• Make SoCs flexible with embedded FPGA (Dec. 01, 2016)
  Embedding an FPGA array can add vital flexibility to SoC designs.
  
  
• Microcontroller Architects Look to Embedded FPGAs for Flexibility (Nov. 24, 2016)
  Today, microcontroller families typically have dozens of versions that have various combinations of GPIO configurations: SPIs, UARTs, I2Cs, etc. to address the needs of different customers. This requires mask changes for each version. A new version takes quarters to go through the design and verification process. Now that microcontrollers are moving to the 40nm node where mask costs are ~$1M, a new solution is required.
  
  
• Do SoC Architects Have to Get Physical? (Nov. 14, 2016)
  With the rapid adoption of the 16/14nm FinFET semiconductor manufacturing processes, the SoC architect’s job is becoming more difficult.
  
  
• Fully-programmable SoCs -- A new breed of devices (Nov. 14, 2016)
  Generally, silicon devices that process information can be classified as being either SoCs, ASICs/ASSPs, or FPGAs. It is very difficult to perform power, performance, and cost comparisons between these technologies without looking at specific applications and running benchmarks. However, it may be possible to take an application and map it to comparable devices in the three categories.
  
  
• Next-generation military radio systems (Nov. 14, 2016)
  With the technological challenges surrounding Software Defined Radio (SDR) largely overcome, the deployment of first generation sets is underway. Possible enhancements such as increasing the bandwidth while simultaneously reducing the size, weight, power, and cost of the device have yet to be developed. Beyond this, Cognitive Radio represents the next major advance in wireless technology, holding out the tantalizing promise of significantly greater spectrum utilization, however, there are some significant barriers which still must be surmounted.
  
  
• A Look at New Open Standards to Improve Reliability and Redundancy of Automotive Ethernet (Nov. 10, 2016)
  To meet the safety and deterministic latency requirements for controlling a car, a new set of open standards is being developed, collectively referred to as “Time Sensitive Networking,” or TSN. These improve the reliability, timing, redundancy, and failure detection ability of Ethernet to the level where it can be applied throughout an automobile. This article describes how Cadence has addressed the hardware requirements of TSN in its Automotive Ethernet Media Access Controller (MAC).
  
  
• Adaptive Rate Control Algorithm (Oct. 31, 2016)
  Ethernet over the last few years has evolved to provide high bandwidth over the aggregate Gigabit link. Next generation telecommunication networks are also shifting towards packet processed network which is enveloped by Ethernet. Citing higher demand for faster and wider Ethernet network, it has become absolutely eminent to study factors holding bandwidth efficiencies of these networks.
  
  
• Pairing Sensitive RF with Voltage Regulators for Noise-Free IoT Modules (Oct. 24, 2016)
  This article presents the challenge of pairing an RF analog circuit with the appropriate inductor-based embedded Switching Regulator (namely eSR, equivalent to on-board DC/DC) allowing to meet both the power efficiency requirements and the module performance level at the same time.
  
  
• Mission Critical in Auto SoC: Interconnect IP (Oct. 24, 2016)
  The average number of IP cores integrated into automotive SoCs is growing from about 20 today to more than 100 within the next five to ten years.
  
  
• The basics of Bluetooth Low Energy (BLE) (Oct. 17, 2016)
  Bluetooth technology has revolutionized wireless communications between devices with its ubiquitous and simple characteristics. It allows devices to communicate without cables while maintaining high levels of security. Because of its low power and low cost, Bluetooth has played a pivotal role in the evolution of applications from high-speed automotive devices to complex medical devices.
  
  
• Power Tips: USB Power Delivery for Automotive Systems (Oct. 14, 2016)
  The new USB Type-C standard has a power delivery portion that could enable portable devices to charge faster.
  
  
• Timing Closure in the FinFET Era (Oct. 10, 2016)
  Achieving system-on-chip (SoC) timing closure is a major obstacle in the FinFET era. Even though designers can now use faster transistors that consume and leak less power than before, FinFET technology does not address the on-chip communications infrastructure or metal line resistance/capacitance issues that negatively impact timing closure.
  
  
• Providing USB Type-C connectivity - What you need to know (Oct. 06, 2016)
  USB Type-C promises to be the answer to all our high-speed serial connectivity dreams, and more. Headlines have trumpeted its higher speeds and an increased power delivery capability, but what has probably captured most people’s attention is the fully reversible connector design, which is neither keyed nor needs different connectors at opposite of a cable.