D&R Industry Articles | Most Popular | SoC News Alerts |

IP / SOC Products Articles

• Learning how to learn: Toddlers vs. neural networks (Sep. 28, 2016)
  It's undeniable that machine learning has made enormous progress over the past few years: from amazing artificial intelligence accomplishments like defeating a top ranking player at the ancient and complex game of Go, to simple everyday uses like auto-tagging personal photo collections.
  
  
• A Virtual Reality Camera Design with 16 Full HD Video Inputs Sharing a Single DRAM Chip (Sep. 05, 2016)
  This paper will describe a realistic design that allows the real time H.264 compression of 16 full HD (1080p@30) video streams, using both I and P frames, sharing the bandwidth of a single DDR3 DRAM chip with 16 bit data bus. This can be achieved thanks to Ocean Logic's proprietary Compressed Frame Store (CFS) technology that allows perfect reconstruction of the compressed frame store data with compression ratios of 10-20:1.
  
  
• Resets in FPGA & ASIC control and data paths (Sep. 05, 2016)
  Reset is an important mechanism to bring a digital system into a known state. The need for reset is governed by the system design and application, and various data and control paths are designed to use a reset signal. Flip-flops in the control path should have reset parameters to bring the system to a known state, while one can usually do without reset in the data path. Let’s discuss various use cases of resets in ASICs and FPGAs.
  
  
• ARM intrusive debugging for post-silicon SoC validation (Aug. 31, 2016)
  Debugging large RTL projects has become increasingly complex. With different types of applications evolving, there is a need for different ways to enable debug hooks in every application. Although the debug architecture of the SOC is at par with its complex design to make non-intrusive debugs easy, but there are multiple scenarios which require intrusive debugging. This article compiles a few scenarios which depict the use of intrusive debugging for validation of an SOC.
  
  
• LTE Single Carrier DFT: Faster Circuits with Reduced FPGA LUT/Register Usage (Aug. 22, 2016)
  Given the prominence of the LTE protocol in wireless devices, it is surprising that there are very few DFT FPGA circuit implementations from which to choose. This is likely due to the complexity of the circuit, which must accommodate run-time choice of many and large non-power-of-two transforms, requiring multiple radices for efficient DFT calculation.
  
  
• Automotive Is the New Black (Aug. 12, 2016)
  If you are designing a tailored automotive chip but new to the market, here's a newbie's guide to selecting processor IP for safety-critical applications.
  
  
• Think Big for Ultra-Low Power IoT SoCs (Aug. 04, 2016)
  Some of the best ideas in creating breakthrough IoT innovation could be gleaned from the design of much larger SoCs.
  
  
• Darwin Comes to Cable (Jul. 28, 2016)
  Pause a moment, if you will, to consider the plight of the oft-reviled cable television providers. At their roots, these companies operated essentially unidirectional networks of coaxial cable for distributing analog video signals to homes. That was then.
  
  
• Choosing a mobile-storage interface: eMMC or UFS (Jul. 26, 2016)
  It is easy to forget just how rapidly the mobile landscape has evolved. Consider that just twelve short years ago, the Motorola Razr was released. With a 0.3-megapixel camera, a 176×220 screen, and five megabytes of embedded storage, this sleek feature phone was a global sensation, with 110 million devices sold worldwide.
  
  
• Setting up secure VPN connections with cryptography offloaded to your Altera SoC FPGA (Jul. 11, 2016)
  In this white paper, we’ll explain the benefits of offloading cryptography routines to hardware. As an example platform, we consider the Cyclone® V SoC device, an Altera® FPGA. Key here is selecting the right IP blocks and installing the appropriate Linux drivers that drive the hardware and allow for an easy integration in your application. Next to being more secure, hardware cryptography is also much faster. A comparison of hardware and software security routines on the Cyclone V SoC shows a gain of 30X for typical Ethernet packets of 1.5 Kbytes.
  
  
• Synchronizing sample clocks of a data converter array (Jul. 01, 2016)
  This article provides a real-life case study of how to build a flexible and re-programmable clock expansion network, that maintains not only an excellent phase noise/jitter performance, but also passes-on the required synchronization information from the 1st device of the clock tree to the last one with deterministic control.
  
  
• Easing Heterogeneous Cache Coherent SoC Design using Arteris' Ncore Interconnect (Jun. 20, 2016)
  Heterogeneous processing has become a hallmark of mobile SoCs, but designing cache coherency across these diverse processing elements can be difficult. Standard on-chip interfaces and network-on-a-chip (NoC) technology are the first step, giving architects IP to efficiently connect compute processing elements as different as CPUs, GPUs, and DSPs. Hardware IP to enable coherent communication between different types of compute engines is the next step. This white paper describes how Arteris’ Ncore IP can help architects design processors fully supporting coherency between heterogeneous elements.
  
  
• What's in the Future for High-Speed SerDes? (Jun. 16, 2016)
  High-speed SerDes interfaces are the gateway for data traffic and analysis on the cloud. End-users want a faster connection to their data. They want to download and stream HD movies as fast as possible. They also want to seamlessly share huge databases. This need for speed directly drives SerDes innovation. In the datacenter market and in the enterprise market, it’s extremely important to have a fast connection.
  
  
• Fronthaul Evolution Toward 5G: Standards and Proof of Concepts (Jun. 13, 2016)
  This paper will help to navigate through the key concepts of packet based Fronthaul and discuss the implications of the adoption of latest Time-Sensitive-Network (TSN) IEEE 802.1CM standard, the IEEE P1904.3 Radio over Ethernet (RoE) standard and latest Next Generation Fronthaul Interface, (NGFI) IEEE P1914.1 initiatives. Finally, a look at the PoC platforms enabled by Xilinx technology and IP offering from Comcores will be offered.
  
  
• Lossless Medical Video Compression Using HEVC (Jun. 06, 2016)
  This paper outlines lossless encoding mode of HEVC and how using lossless encoding mode, compression ratio of more than 2 (2:1) can be achieved.
  
  
• Custom Corner Characterization for Optimal ASIC/SoC Designs (May. 26, 2016)
  Today's characterization tools offer a very good solution for extracting the best performance out of an ASIC/SoC for any specified PVT operating conditions.
  
  
• Building Multi-Port USB Type-C Adapters for Power (May. 23, 2016)
  In the a previous blog, we discussed some of the challenges when designing AC/DC adapters for USB Type-C power delivery (PD). In that article, we focused on an adapter with a single Type-C output connector. In this article, we'll examine the complexities introduced when architecting a multi-port Type-C adapter.
  
  
• Security Considerations For Bluetooth Smart Devices (May. 09, 2016)
  Bluetooth Smart is an emerging short range wireless technology aimed for low power devices. Bluetooth 4.2 core specification provides various methods to secure the communication between devices and establish trusted connections. This paper describes the design considerations to secure the Bluetooth smart devices.
  
  
• Control an FPGA bus without using the processor (Apr. 28, 2016)
  A bit of added hardware lets FPGA engineers access peripherals without having to deal with the processor.
  
  
• Careful IP Integration Key to First-Pass Silicon (Apr. 26, 2016)
  Most ASIC companies today rely on third-party IP in building a custom ASIC/SoC. While ensuring convenience in terms of flexibility, schedule, and cost effectiveness, however, this approach can also present challenges
  
  
• Foundation IP for 7nm FinFETs: Design and Implementation (Apr. 18, 2016)
  Learn about the challenges of IP design and implementation for 7nm FinFETs. Along with the performance and area benefits that the node brings, designers must understand the significant technical challenges stemming from increasing variability associated with tighter pitches and more complex lithography steps. Design for variability and reliability considerations will require comprehensive modeling and analysis as well as advanced circuit techniques such as on chip sensing and compensation.
  
  
• Guide to Choosing the Best DCDC Converter for Your Application (Mar. 28, 2016)
  This white paper introduces a procedure for choosing the proper DCDC switching converter for a given application. It explains basic, performance, and optional metrics in detail. It also demonstrates other practical aspects that are sometimes overlooked by system designers. Multiple application examples are provided.
  
  
• NVMe IP for Enterprise SSD (Mar. 24, 2016)
  Most of SSD manufacturers jumped into this new storage market with flash-based technology. A second wave of products will come in the near future, using a new generation of non-volatile memories, delivering impressive speed performances compared to NandFlash memories. The SSD manufacturers will have to deal with low latency SSD controller design in order to benefit from the new NVM features, while keeping high reliability and low power consumption. This white paper proposes a solution based on a full hardware NVMe implementation, describing its architecture, implementation and characterization.
  
  
• LPDDR4: Now and for Next Generation (Mar. 14, 2016)
  Technology has leapt several folds. Looking at the communication industry, it has steadily advanced from the heavy gadgets that had only calling and texting facilities, a poor battery life only made matters worse. This industry however has led to many research works and innovations, the phones that were once meant only for calling are now capable of doing so much, calling is now a secondary feature. Mobile device user is using so many applications in parallel which in turns demands more powerful processing unit and faster, bigger memory.
  
  
• A versatile Control Network of power domains in a low power SoC (Mar. 10, 2016)
  Developing and verifying a control network in a low-power SoC is a challenging task, especially managing the different states of regulators and modes of power domains. This article first describes state-of-the-art approaches to addressing this issue, and then delves into the solution promoted by Dolphin Integration to go further, thanks to the easy and secure Maestro� solution to manage SoC power mode transitions.
  
  
• D32PRO, scalable & royalty free 32-bit CPU (Mar. 03, 2016)
  D32PRO is one of the newest 32-bit CPUs available on the market. It’s been designed by Digital Core Design, IP Core provider and SoC design house from Poland, responsible e.g. for the world’s fastest or world’s smallest 8051 CPU. DCD launched more than 70 different architectures since 1999, which have been implemented in more than 300 000 000 electronic devices, that’s why one can be sure that quite considerable experience stands behind the D32PRO.
  
  
• It's Alive! The Miraculous Resurrection of Artificial Intelligence (Feb. 29, 2016)
  New results on fronts as diverse as playing human games, identifying photos of objects, showing awareness of situations, and control of autonomous vehicles are all showing promise. Will this time be different?
  
  
• Designing AC/DC Adaptors for USB Type-C Power (Feb. 29, 2016)
  After much discussion, products with new USB Type-C (Type-C) ports are finally here! In 2015, Apple's new MacBook and Google's Nexus 6P were released with the new USB-C port.
  
  
• Designing an Efficient DSP Solution: Choosing the Right Processor and Software Development Toolchain (Feb. 22, 2016)
  This white paper describes how to generate tight, efficient, and maintainable DSP code for a platform consisting of an IP core based on a specialized instruction-set architecture (ISA) coupled with a DSP-aware toolchain.
  
  
• Securing the Most Important Goal of USB Type-C Technology: A Better User Experience (Feb. 17, 2016)
  Now that the USB Type-C™ Cable and Connector Specification is starting to reach the masses, the world of advanced technology and hundred-pages-thick specifications finally meets the world of casual users. The initial impression is that while device owners appreciate the new features and ease of use, they are more puzzled than before with incompatibility of devices, dangerously bad cables, and the need for adapters for their old devices. What do we, as an industry, need to do to overcome these fears and secure a path to USB Type-C success?