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IP / SOC Products Articles

• Leverage always-on voice trigger IP to reach ultra-low power consumption in voice-controlled devices (Feb. 15, 2016)
  Due to the lack of thorough specifications to assess the performance of voice detection solutions, it is a real conundrum for users to evaluate the best solution among a jungle of true and false detection claims and without any benchmark. ?The aim of this article is to help IP procurement managers, SoC architects and system makers using voice detection IP in their systems to assess and compare the detection performances.
  
  
• Delivering High Quality Analog Video Signals With Optimized Video DACs (Feb. 15, 2016)
  This paper outlines the most common analog video signal standard-specifications that multimedia SoCs must support. It describes the key characteristics and features of a DAC solution optimized for video applications. The paper addresses system-level techniques that together with an optimized video DAC will enable SoC designers to deliver power-efficient and feature-rich multimedia devices.
  
  
• Custom ASICs for Internet of Industrial Things (IoIT) (Feb. 11, 2016)
  This white paper commences with an overview of the IoIT (Internet of Industrial Things) opportunity, the market drivers, and how the semiconductor industry is responding to this need. We then include an example of a customisable SoC intended for use in various industrial applications where low power consumption, remote deployment, reduced production costs and short time-to-market are vital.
  
  
• Optimizing LPDDR4 Performance and Power with Multi-Channel Architectures (Feb. 08, 2016)
  
  
  
• Opportunities and Challenges for Near-Threshold Technology in End-Point SoCs for the Internet of Things (Feb. 04, 2016)
  Qian Yu, Technical Marketing Manager at ARM, discusses the potential of near-threshold technology to enable the lowest possible power consumption to extend battery life for end-point devices deployed in the Internet of Things. He also reviews some of the challenges including integrating memory and attaining necessary support from semiconductor foundries and EDA vendors to make ultra-low-power, near-threshold design a reality.
  
  
• Interconnect: Switzerland of IP (Feb. 01, 2016)
  The IP and EDA industries need an independent, neutral provider of interconnect IP technology to provide a level playing field for other IP companies
  
  
• Addressing Three Critical Challenges of USB Type-C Implementation (Feb. 01, 2016)
  As designers create new products and system-on-chips (SoCs) with USB Type-C support, they need to be aware of datapath and hardware/software partitioning challenges.
  
  
• Reusable MAC Design for Various Wireless Connectivity Protocols (Jan. 25, 2016)
  This paper presents how the 8-bit customized micro-processor could implement the MAC operation that sufficiently co-processes with main CPU as well as meets the timing requirement for controlling various PHY and RF. Because IEEE 802.11ac VHT MAC is the most challengeable protocol to be designed by SW among the introduced connectivity technologies, we evaluated our MAC design with VHT MAC protocol and generated several constraints, which are not critical points to our programmable and common platform concepts.
  
  
• How a 16Gbps Multi-link, Multi-protocol SerDes PHY Can Transform Datacenter Connectivity (Jan. 21, 2016)
  Increasingly, more of the focus on mobile has centered around cloud datacenters and the networking to get the data back and forth between these datacenters and the mobile device. Functions like voice recognition and mapping depend on the ability to split the functionality between the smartphone, for local processing like encryption and compression, and the back end, where a large number of servers can do the heavier lifting before returning the results.
  
  
• True Random Number Generators for Truly Secure Systems (Jan. 18, 2016)
  Random numbers form the basis, or root, of most security systems. Yet the methods for generating random numbers vary widely in practice as well as efficacy.
  
  
• NoC Interconnect Fabric IP Improves SoC Power, Performance and Area (Jan. 18, 2016)
  Imagine you have defined the structure of a system-on-chip and now you have to assemble all the IP blocks and make them communicate on the die. You have spent months rigorously selecting SoC IP that reflects the desired chip functionality. However, without the on-chip interconnect fabric it is just a collection of isolated blocks.
  
  
• Modeling and Verification of Mixed Signal IP using SystemVerilog in Virtuoso and NCsim (Jan. 11, 2016)
  In this paper we present a methodology to model and verify a mixed-signal IP using SystemVerilog in Virtuoso and NCsim. We take our 12.5Gbps transmitter (TX) design as an example to explain the method we propose. This TX is designed to operate at programmable data rates from 1.25Gbps – 12.5Gbps and to support requirements of multiple serial protocols like USB, PCIe, and SATA. Interaction between AFE and Digital is key towards proper implementation of features like Feed Forward Equalization (FFE), programmable output swing and power management states.
  
  
• DFT strategy for IPs (Jan. 11, 2016)
  IPs (Building blocks of ASIC/SoC e.g. CPU, GPU) build and sign off in a wider sense. It doesn’t always mean Chip Timing, Design Rule Constraints & Power Closure of a block, but also refers to the creation of a layout/partition around the delivered build/sign off IPs/blocks. This would further refer to flows that are planned, library composition, various floorplan styles and shapes.
  
  
• Enable IoT ASIC Design Using Platforms (Jan. 08, 2016)
  The Internet of Things (IoT) hype is now getting real. This, in turn, is creating the opportunity to move from off-the-shelf chip designs to custom silicon. The key to creating cost-effective, custom silicon for the IoT will be the platform approach.
  
  
• USB Type-C: Is it all just Hype-C for embedded designers? (Dec. 14, 2015)
  Will the do-it-all connector standard maintain its blazing fast adoption?
  
  
• Tech Overhaul: An Ode to Faster Memories (Dec. 14, 2015)
  With the advent of technology the globe is shrinking. Technology has leapt many bounds and brought almost everything thinkable at one’s fingertips. Amongst various spheres of Technology the communication industry takes the cake, for every advent here is awaited with bated breath.
  
  
• Soft-Decoding in LDPC based SSD Controllers (Dec. 08, 2015)
  What happens when that initial decode fails? How soft data can be used to recover data on the SSD.
  
  
• How to Ensure a Bug Free BootROM? (Nov. 30, 2015)
  In this article, we outline the robust testing of BootROM by churning out best capabilities of three powerful platforms – SoC simulation, Hardware emulation, and EVB Validation.
  
  
• Breakthrough in Microprocessor Architecture and Energy Performance (Nov. 26, 2015)
  Radically new processor architecture, reducing overhead high frequency switching, is needed in order to fully utilize the potential of future CMOS technology. Optimizing for energy efficiency, performance, cost, code density, adaptability and scalability are big challenges for the microprocessor architect. Imsys has developed a dual core processor with features not found in other architectures and it is runtime reconfigurable.
  
  
• Efficient logic optimization utilizing complementary behavior of CMOS gates (Nov. 23, 2015)
  Any typical digital design style with CMOS uses complementary pairs of p-type and n-type MOSFETs for logic functions implementation. Naturally, CMOS always ought to provide INVERTED outputs like Inverter, NAND, NOR etc. Sometimes a non-inverting function is required, in which case it's just as easy to implement it with a final inverter or with a non-inverting function like AND, OR.
  
  
• Safety in SoCs: Accelerating the Road to ISO 26262 Certification for the ARC EM Processor (Nov. 23, 2015)
  This white paper outlines the key requirements for ISO 26262 certification and demonstrates how to accelerate the development of safety-critical IP and SoCs through the use of out-of-the-box safety-ready IP with advanced verification qualification tools and methodologies.
  
  
• Design trade-offs of using SAR and Sigma Delta Converters for Multiplexed Data Acquisition Systems (Nov. 18, 2015)
  Multiplexed data acquisition systems (DAS) utilized in industrial process control, portable medical devices and optical transceivers need increased channel density, where the user wants to measure the signals from multiple sensors and monitor and scan many input channels in to a single or several ADCs.
  
  
• Low-complexity compression solves video challenges (Nov. 16, 2015)
  Advances in image sensors and camera technology promise to make your video applications more sensitive, with better-quality images at higher frame rates. However, this also means that more bits have to be streamed, analyzed, kept in memory, or stored for archiving. In short, you’ll need more bandwidth, expensive cabling, and new storage solutions. A smart solution to avoid these challenges is to use a lightweight, mezzanine compression, a compression that allows transporting and storing video at high quality but also at a reasonable cost, possibly even on your existing equipment.
  
  
• Greater Debug of a SoC having heterogeneous ARM Core's (Nov. 09, 2015)
  This article describes a high visibility and non-invasive debug architecture having Quad Core ARM Cortex A9 and Dual Core ARM cortex R4 cores. This debug architecture implements ARM Coresight components to enable seamless debug capability and external trace support. ARM Coresight technology and the components are re-used for debug purposes in various SOC’s having ARM cores.
  
  
• USB 3.1 implementation of USB Type-C (Nov. 05, 2015)
  This article discusses how to implement a USB Type-C port so that it will minimally impact an existing system.
  
  
• Complex SoCs: Early Use of Physical Design Info Shortens Timing Closure (Nov. 02, 2015)
  Chip designs are becoming so complex that they are extremely difficult to implement in the physical design stage. Predicting trouble spots beforehand is paramount.
  
  
• Firmware Compression for Lower Energy and Faster Boot in IoT Devices (Oct. 26, 2015)
  The phrase “IoT” for Internet of Things has exploded to cover a wide range of different applications and diverse devices with very different requirements. Most observers, however, would agree that low energy consumption is a key element for IoT, as many of these devices must run on batteries or harvest energy from the environment.
  
  
• Designing High Performance Interposers with 3-port and 6-port S-parameters (Oct. 19, 2015)
  This paper will interpret multiport S-parameters for several memory interposer design cases. This will help the audience understand some of the performance characteristics that can be inferred from the S-parameters, as well as some of the interactions between the interposer and the device under test and probing system
  
  
• Architect a Next-Gen 802.11ac Wave 3 Software-Defined Modem (Oct. 12, 2015)
  This paper presents an evolution of the RivieraWaves Stream architecture for next-generation 802.11 ac Wave 3, which can support complex configurations up to 8x8 MU-MIMO with 160MHz bandwidth.
  
  
• Supply Noise Induced Jitter - Don't Let it Kill your Chip (Sep. 28, 2015)
  This presentation is about a problem we at Silicon Creations have seen quite often when our, or others’ PLLs are used in complex SoCs. Although the design team usually implements the PLL correctly in the chip with the right supplies connected the right ways, we have often seen that designers overlook the significant impact that their floorplan and power supply plan have on the clock as it travels from the PLL to the circuits the PLL is clocking.