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IP / SOC Products Articles

• USB 3.1 Gen 2 Brings Higher Data Rates with Architecture Improvements (Sep. 28, 2015)
  In this article, let's take a closer look at the application architecture impact of the USB 3.1 specification - namely, the changes that need to be introduced to take advantage of the improved bandwidth that you can get from integrating USB 3.1 Gen 2 support in your designs.
  
  
• Methods to Fine-Tune Power Consumption of PCIe devices (Sep. 21, 2015)
  This paper will examine the various design elements, design techniques and PCI Express optional features that can be leveraged to reduce a device’s power consumption without compromising performance.
  
  
• Implementing Ultra Low Latency Data Center Services with Programmable Logic (Sep. 21, 2015)
  Data centers require many low-level network services to implement high-level applications. Key-Value Store (KVS) is a critical service that associates values with keys and allows machines to share these associations over a network. Most existing KVS systems run in software and scale out by running parallel processes on multiple microprocessor cores to increase throughput.
  
  
• LBIST - A technique for infield safety (Sep. 21, 2015)
  In this article, we will be discussing how LBIST testing differs from conventional testing, some important applications of LBIST and design overhead of using LBIST in the design.
  
  
• All you need to know about MIPI D-PHY RX (Sep. 16, 2015)
  MIPI D’Phy, a physical serial communicating layer connecting the application processor to the display device or the camera, offers advantages as the physical layer.
  
  
• UFS Goes Mainstream (Sep. 14, 2015)
  UniversalFlash Storage (UFS) was created for mobile applications and computer systems requiring high performance and low power consumption. These systems typically use embedded Flash based on the JEDEC standard eMMC. UFS was defined by JEDEC as the evolutionary replacement for eMMC offering significantly higher memory bandwidth. The standard builds on existing standards such as the SCSI command set, the MIPI Alliance M-PHY and UniPro as well as eMMC form factors to simplify adoption and development.
  
  
• Anatomy of the HDMI IP Certification Flow (Sep. 07, 2015)
  This white paper outlines the HDMI IP certification flow from internal quality, functionality and interoperability testing to certification of the latest HDMI Compliance Test Specification (CTS) at an Authorized Test Center (ATC).
  
  
• An Automated Flow for Reset Connectivity Checks in Complex SoCs having Multiple Power Domains (Sep. 07, 2015)
  Today’s SoC designers are designing chips which have an optimum balance between performance and power numbers. So, the whole SoC design is divided into different power domains having a set of modules present in each of them. The power domains can be kept powered-on in some modes of operations and can be power gated in some other modes of operations.
  
  
• Meeting IP Requirements of New Auto SoCs (Sep. 03, 2015)
  To implement the advanced protocols required to meet high performance operation, the ADAS SoCs use design and process technologies that are more stringent than most high-end consumer applications.
  
  
• Method for Booting ARM Based Multi-Core SoCs (Aug. 31, 2015)
  In the boot process various modules/peripherals (like clock controller or security handing module and other master/slaves) initialized as per the SoC architecture and customer applications. In Multi core SoCs, first primary core (also called booting core) start up in boot process and then secondary cores are enabled by software.
  
  
• USB Power Delivery 2.0 Enables Power Distribution Flexibility (Aug. 31, 2015)
  The latest USB 3.1 specification increases the current capability to 900mA if legacy Type-A connectors are used. If the new Type-C connector - which has four power/ground pairs - is employed with USB 3.x, the current rating can be as high as 3A, but still at only 5V.
  
  
• Save power in IoT SoCs by leveraging ADC characteristics (Aug. 27, 2015)
  Power-sensitive applications such as Internet-of-Things (IoT) require a comprehensive power savings strategy within the system-on-chip (SoC). Techniques relying solely on the use of traditional power down modes and low supply voltage may not be enough to achieve the required power targets. The analog block is often assumed to be too sensitive and not compatible with aggressive power management techniques.
  
  
• Clock Gating Checks on Multiplexers (Aug. 24, 2015)
  With the increasing complexity of design in today’s fast changing world, the thrust on power saving has increased manifold. Consequently, gating the most toggling signal on the SoC i.e. the clock has become the norm now rather than an exception. From timing perspective, clock gating brings some challenges and some special considerations.
  
  
• PLL Subsystem architectures for SoC design (Aug. 24, 2015)
  Because of the cornerstone importance of PLLs to an SoC design, this article considers the various challenges in the design of PLL subsystems, and discuss architectural solutions.
  
  
• 7 Steps to a Successful Analog ASIC (Aug. 20, 2015)
  I’m willing to bet that there are tens of thousands of analog applications out there that would benefit financially from ASIC integration. So what’s the holdup? Based on my 40+ years in the Analog IC business, I can boil it down to one word. Misinformation. This is a combination of a lack of information, incorrect information, and of course, FUD (Fear, Uncertainty and Doubt).
  
  
• High Speed ADC Data Transfer (Aug. 17, 2015)
  When continuously running a high speed ADC, it can be a challenge to deal with the firehose of raw data available at the output. To use City Semiconductor’s 2.5 GS/s 12-bit ADC, for example, 30 gigabits per second of data have to be accepted.
  
  
• Motion Picture: a Reality on Emulation Platform (Aug. 17, 2015)
  In present day’s situation, whenever we are in the phase of designing a cluster SoC, we have no reliable way of verifying our design in real case scenarios, or showcase the possibilities of our design through any demos. This, sometimes, paves way for critical design bugs which requires re-spins/cuts.
  
  
• Floating-point FFT with Minimal Hardware (Aug. 10, 2015)
  Here we discuss Centar’s floating-point FFT technology which provides IEEE754 single-precision outputs, yet is much more hardware efficient. For example in the FPGA domain, which is the focus of this note, comparisons show that other designs use up to 100% more logic elements. Such reduced hardware can move the tradeoffs between fixed and floating-point attractively in the direction of the floating-point option. Centar’s design also has better numerical properties.
  
  
• Effective Timing Strategies for Increasing PCIe Data Rates (Jul. 30, 2015)
  The PCIe standard has become a popular choice for high-speed serial communication but as successive generations of the standard offer increased data rates, reference clock performance is becoming progressively more critical and the specifications more aggressive to ensure good timing margins.
  
  
• Chips in Space -- MacSpace, A Record Throughput Multi-Core Processor for Satellites (Jul. 30, 2015)
  MacSpace is a collaborative R&D project aiming to research and develop a many-core DSP chip and computer for use in space.
  
  
• The Hard Facts about Soft Interconnect IP (Jul. 27, 2015)
  Building world-class Network-on-Chip interconnect IP and configuration tools is difficult, time consuming and capital intensive
  
  
• Cheaper, Denser NAND Requires Better Error Correction (Jul. 22, 2015)
  Here's why PMC-Sierra switched from Bose-Chaudhuri-Hocquenghem codes to low-density parity check (LDPC) codes for error correction in its solid-state drive controllers.
  
  
• Device Malfunction due to Faulty Digital circuit along with suggested Remedies (Jul. 20, 2015)
  Using of basic building blocks in different ways to make complex circuit is a common axiom in Digital Logic design. The complexity of these building blocks can vary from simple structure like synchronizers, multiplexers, adders, FIFO, Glitch-free multiplexer to complex circuits like custom CDC Module, Encoders, decoders etc.. If we talk about these circuits, there exist countless designs, each of them depending on the requirement- any implementation working in one scenario may fail or put limitations in other scenario. This paper intends to discuss some of the commonly used circuits which are faulty in certain scenario and various remedies to make those circuits more robust to increase their acceptability.
  
  
• The Evolution of Object Recognition in Embedded Computer Vision (Jul. 13, 2015)
  Object detection and recognition are an integral part of computer vision systems. In computer vision, the work begins with a breakdown of the scene into components that a computer can see and analyse.
  
  
• Debugging LBIST safe-stating issues (Jul. 13, 2015)
  Logic built-in self test (LBIST) allows hardware to test its own operation. There is no need for any external hardware or test equipment. LBIST is a “must have” feature for safety compliant SoCs. But care must be exercised when using LBIST in a complex SoC.
  
  
• Configurable Asynchronous Set/Reset Flip-Flop for Post-Silicon ECOs (Jul. 06, 2015)
  This paper proposes a configurable asynchronous set/reset flip-flop design that tends to resolve the timing and implementation issues concerned with such post-silicon metal ECOs and compares the existing solutions against the proposed one to evaluate its benefits.
  
  
• Reset connectivity checks in complex low power architectures (Jul. 06, 2015)
  In this article we are explaining the checks that should be done to catch such power domain related reset connectivity issues.
  
  
• Ethernet as IP: The Time Has Come (Jun. 29, 2015)
  In this paper, we will look at the economics of integrating the Ethernet Physical Layer, and what options exist for product managers and engineers seeking to shrink their power and area footprints, while achieving cost reduction
  
  
• Ten reasons interconnect matters (Jun. 25, 2015)
  Interconnect is the Rodney Dangerfield of IP blocks. It gets no respect. It connects hundreds of disparate IP blocks, each with hundreds of interface signals, and dozens of transaction protocol attributes. It does it in a way that each IP need not know the protocol details of any other. It also provides for the data access requirements of each IP, and does it physically distributed across the chip floorplan. Interconnect fabric technology is sophisticated, and very important for modern chip designs. Following are ten reasons why interconnect matters.
  
  
• Reducing chip IR drop in backward-compatible power bar-limited LQFP SoCs (Jun. 24, 2015)
  SoC design comes with its own set of complications and challenges. One of the biggest challenges that arises is backwards-compatible power bar-limited design in an LQFP package.