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IP / SOC Products Articles

• Efficient methodology for design and verification of Memory ECC error management logic in safety critical SoCs (Jun. 22, 2015)
  This paper presents the efficient methodology to implement and verify ECC error management in systems with large number of memories, with minimum hardware overhead and without compromising the safety requirements.
  
  
• High Speed Data Recorder (Jun. 15, 2015)
  A new IP Core from ASICS World Services, provides a complete high speed data recorder, in one easy to use block.
  
  
• An efficient way of loading data packets and checking data integrity of memories in SoC verification environment (Jun. 08, 2015)
  This paper discusses about the requirement for backdoor loading and comparison of processed data (in digital verification environment) and explains a method to implement such a scheme, which saves a lot of simulation time, while maintaining the data integrity.
  
  
• A Case Study - RF ASIC Validation of a satellite transceiver (May. 27, 2015)
  ASIC validation in the RF world comes with its own set of hurdles and challenges, with high quality lab equipment, experience and know-how essential. A recently completed RF sub-system validation at S3 Group is presented in the form of a case study of the execution.
  
  
• Safety intended Re-configurable Automotive microcontroller with reduced boot-up time (May. 21, 2015)
  This paper addresses these issues associated with partial power failures. It proposes a technique using which the user can get a basic warning that there is a failure and can also diagnose the problem, enhancing safety. Also the user can run small applications if needed.
  
  
• Latest Version of Interface Protocol Speeds Mobile Device Development, Lowers e-BoM (May. 18, 2015)
  Originally designed for mobile devices with limited power and high functionality, LLI technology is now applicable to a broader range of devices that require improved chip-to-chip functionality between master and companion chips. LLI v2.1 allows two devices on separate chips to communicate as if a device attached to the remote chip actually resides on the local chip. This allows memory sharing between chips, which reduce the electronic bill of materials (e-BoM).
  
  
• Verification Challenges of High Speed Interfaces (May. 18, 2015)
  This paper talks about the Pre-Si verification challenges of JESDPHY, USB PHY; the solutions we came up with; and the bugs that were caught in the early in the design cycle with our approach.
  
  
• Design Implications of USB Type-C (May. 13, 2015)
  USB Type-C is a very big deal for the USB community and IP developers. What are the gotchas? Is there no pain with this gain?
  
  
• How Random is Random Enough For Cryptography? (May. 12, 2015)
  How can one create a random stream of bits suitable for use in encryption and embed this solution in an FPGA?
  
  
• A High Efficiency Referencing Frame Buffer Compression IP for H.265 Video Codec (May. 11, 2015)
  A 3.0X times image compression method and fast storage device accessing H.265 referencing image frame is achieved by applying fixed bit rate to reduce each “Block of pixels” data of each image frame. Several thresholds are quality predetermined depending on the availability of the bandwidth of the storage device and the image resolution to decide the compression ratio of each image frame
  
  
• Risks and Precautions to take care while using On-Chip temperature sensors in Safety critical automotive applications (May. 11, 2015)
  Automotive electronics have to sustain harsh conditions like temperature and noisy Environment. The aim these days is to place the electronics as near to engine and transmission control unit as possible so that their noise effect is minimal. This in turn creates another challenge that electronics have to survive very high temperature as engine and transmission control unit can raise the temperature significantly.
  
  
• A look into Bluetooth v4.2 for Low Energy Products (May. 05, 2015)
  The Bluetooth v4.2 Specification was officially adopted in December of 2014 by the Bluetooth Special Interest Group (Bluetooth SIG) and it brings a host of updates to Bluetooth Low Energy (BLE) or Low Energy (LE) for short. Although no Bluetooth chipset vendor is officially supporting it yet, support will make its way into devices in the next few quarters. There are quite a few updates in the v4.2 specification, and we’re going to go over them and how they can affect your product and design decisions.
  
  
• Efficient methodology for verification of Dynamic Frequency Scaling of clocks in SoC (May. 04, 2015)
  In this paper, an approach has been given to verify the integration and functionality of Dynamic Frequency Scaling in the SoC using multiple checks like assertions, frequency monitors and randomized test cases which we can use in the testbench environment. With this approach, multiple design bugs have been uncovered in the SoCs.
  
  
• Rethinking the Internet of Things (Apr. 30, 2015)
  As the Internet of Things (IoT) cements itself into place as the mandatory next big thing for 2015, more systems architects are taking a hard look at its underlying concepts. As they look, these experts are asking some hard questions about simplistic views of the IoT structure: the clouds of sensors and actuators attached to simple, low-power wireless hubs, linked through the Internet to massive cloud data centers.
  
  
• Method to minimize switching activity in digital data transfer protocols (Apr. 27, 2015)
  Parallel Data transfer using digital hardware involves a significant amount of switching power consumption, which increases as “data activity” increases. The motivation was to reduce switching noise in areas where parallel data packet transfer is involved, e.g., reading sectors of Flash memory, inter-processor communication, etc
  
  
• FPGA-Based NVM Express Flash Storage Cards in the Data Center (Apr. 16, 2015)
  The advent of FPGA-based flash storage cards enables data centers to customize their solution for maximum performance, storage capacity, and flash durability.
  
  
• Product How-to: Fully utilize TSMC’s 28HPC process (Apr. 14, 2015)
  This article describes five areas where designers can take advantage of this new process with the latest logic library technology to optimize the performance, power and area of their system on chips (SoCs).
  
  
• IP and system design lower data centre power consumption (Apr. 13, 2015)
  With mobility, cloud computing, and the Internet of Things becoming increasingly pervasive, businesses are under pressure to increase the energy efficiency of their data centres, warn Arif Khan and Osman Javed, Cadence.
  
  
• How soft errors damage vital information (Apr. 10, 2015)
  Here is how soft errors occur and how they can cause damage to critical data stored in semiconductor memories. The article covers the sources and the likelihood of their occurrence and explains how they impact individual memory cells, causing them to change state
  
  
• CSoC Platform / Digital Subsystem IP for IoT (Apr. 06, 2015)
  This paper describes a CSoC platform and configurable digital subsystem IP which can be deployed for development of IOT edge devices. The paper encompasses the different attributes of IOT edge device that can cater multiple industry segments, key features and benefits of CSoC platform, components of the digital subsystem IP that enables rapid prototyping of SoCs for IOT applications.
  
  
• Interleaved ADC Calibration Techniques (Apr. 02, 2015)
  Commercial time-interleaved ADCs have been available since the early 2000’s. Since then the number of academic and industry-sponsored articles showing the advantages of interleaving has been steadily increasing.
  
  
• When Developing New Silicon IP, Is First Pass Success Possible? (Apr. 02, 2015)
  Brandt Braswell, a distinguished member of the technical staff at Freescale Semiconductor, provides tips to help turn out an IP core that is "right" the first time it appears in silicon.
  
  
• Virtual Prototyping Platform with Flash Memory (Mar. 30, 2015)
  In this paper we will see how the flash memories developed using Carbon Model Studio helps to bring up an ARM® Cortex A7 flash memory sub-system with primary and secondary boot codes. Flash memories system demonstrated here can be used for early boot code and driver development for any CPU based SoC.
  
  
• Building a high-performance, low-power audio/voice subsystem (Mar. 26, 2015)
  With the growing popularity of applications such as mobile gaming and voice triggering, the audio/voice subsystem is playing a prominent role in many mobile system-on-chip (SoC) designs. The subsystem must be designed to meet dual demands: high-performance, high-resolution audio stream processing as well as always-on, low-power voice trigger and recognition. Customizable digital signal processing (DSP) and audio/voice subsystem solution intellectual property (IP) blocks can provide a cost-effective and efficient way to develop and deliver high-performance audio/voice products.
  
  
• When Your Embedded Processor Runs Out of Steam, Try Parallelism (Mar. 24, 2015)
  The scenario is becoming increasingly familiar. You have a working embedded design, perhaps backed by years of deployment with customers and hundreds of thousands of lines of debugged code. Along comes marketing with a new set of performance specifications, or R/D with a new computer-crushing algorithm. Your existing CPU family just can’t handle it.
  
  
• Selecting an Optimized ADC for a Wireless AFE (Mar. 23, 2015)
  Internet enabled mobile devices are continuing to become more prevalent in the modern world. With this proliferation of smart, connected devices – many of which are battery powered – comes a greater need for power efficient wireless transceivers. In addition to meeting stringent power specifications, RF system designers must also ensure that their devices adhere to the latest wireless standards, including Long Term Evolution (LTE) and Wi-Fi.
  
  
• LTE-A Release 12 transmitter architecture: analog integration (Mar. 23, 2015)
  This article explores the analog integration challenges in 4G base stations. Rel-12 features, such as wideband downlink CA, downlink multiple-input multiple-out (MIMO) spatial multiplexing, and AAS with embedded RF, present new design challenges in next-generation eNodeB radios.
  
  
• Dynamically controlled logic gate design for all power modes (Mar. 23, 2015)
  In a current trend of SoC Design, IC’s are becoming more and more complex so the challenges of meeting all the design requirements have become increasingly difficult. Expectations from current SoC’s are low power design and reduced die size with more & more features & hence logic. Though, it is impossible to meet all of these but what designers can ensure is that try to meet all of them to the extent such that there is no loss in other specifications.
  
  
• Defend encryption systems against side-channel attacks (Mar. 17, 2015)
  From its ancient origin as a tool for protecting sensitive wartime or espionage-related messages, cryptography has become a foundational building-block for securing the systems, protocols, and infrastructure that underpin our modern interconnected world. But the physical mechanisms used in performing encryption and decryption can leak information, making it possible to bypass this security. Protecting designs against such side-channel attacks starts with understanding how such attacks operate.
  
  
• The future of the 8051 legacy upgraded for the Internet of Things (IoT) (Mar. 16, 2015)
  The Internet of Things (IoT) is the latest buzzword driving the industry for any number of low-power interconnected things. However, the IoT encompasses an incredible number of different types of things ranging from edge objects, namely smart or wearable devices which are battery powered with sensors and wireless connectivity, through aggregation nodes, namely hubs, routers and gateways for data aggregation, up to information processing servers in the Cloud to handle the data pushed by edge objects.