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IP / SOC Products Articles

• Challenges in LBIST validation for high reliability SoCs (Jul. 22, 2014)
  Logic built-in self test (LBIST) is being used in SoCs for increasing safety and to provide a self-testing capability. LBIST design works on the principle of STUMPS architecture. STUMPS is a nested acronym, standing for Self-Test Using MISR (Multiple Input Signature Register) and Parallel SRSG (Shift Register Sequence Generator).
  
  
• Is Your Processor IP ISO 26262-Compliant? (Jul. 22, 2014)
  At every level in the development of safety systems, from the selection of processor IP and the IP development process, to software development and even document creation, there is a need to address functional safety compliance. Understanding the compliance with ISO 26262 from a processor IP perspective, the role of the processor IP, its software, and its documentation can help ease the certification process.
  
  
• Designing optimal wireless basestation MIMO antennae: Part 1 - Sorting out the confusion (Jul. 21, 2014)
  This article will first review the relevant MIMO modes and technology and the advantages of choosing a suboptimal MLD receiver over a minimal mean square error (MMSE) receiver. It will also explain the complexities of the MLD implementation and how to resolve them using suboptimal ML solutions.
  
  
• Validating and using the I2C protocol (Jul. 17, 2014)
  I2C is a two wire, clock synchronized protocol with a bi directional data line and a uni directional clock line. Its simplicity lies in its use of only two lines for communication and its complexity lies in the fact that these lines are shared among all the devices on the bus. The I2C bus can have several masters and slaves connected on the same two lines and bus arbitration is employed to handle bus contentions. The scope of this article is to bring out some common I2C issues that come up while validating and using the I2C protocol.
  
  
• Reduce SoC verification time through reuse in pre-silicon validation (Jul. 11, 2014)
  A key focus of the IC design industry is to deliver first-pass silicon, which means finding most, if not all, of the potential defects before tape-out. This is extremely difficult due to increasing design complexity, clock speeds, multi-layered software, and shrinking technology and cycle time. Each re-spin of the silicon may cost a company millions of dollars and a lot of wasted time and effort. With more and more third party IP being used in the SoC to shorten time-to-market, the task of finding bugs before silicon becomes more difficult due to limited knowledge of the external IP by the SoC engineers.
  
  
• Define Analog Sensor Interfaces In IoT SoCs (Jul. 03, 2014)
  Also known as “smart everything,” the Internet of Things (IoT) is grabbing headlines across the industry. As any great new technology, it comes wrapped in shiny paper that touts it as the solution for all things connected, be it the online tracking of the merchandise in a truck across the continent, the automatic sensing of the color of toast in the toaster, or measuring the number of steps walked in a day.
  
  
• Guide to Choosing the Best LDO for Your Application (Jun. 23, 2014)
  LDOs are so common inside portable devices, state of the art power management integrated circuits (PMICs) for smartphones and other portable devices include over a dozen LDOs. To know which LDO you need, you must first define the application of your LDO and then examine which parameters are most important when dealing with that application. With so many different LDO applications and the multiple parameters that characterize a particular LDO, it is not easy to determine which LDO is best suited. To help you figure this out, we have put together this reference. This guide presents a comprehensive list of all of the different LDO parameters with definitions, the most common applications of LDOs, and which parameters are critical for each.
  
  
• Application Architectures for FPGA-Based Image Processing (Jun. 20, 2014)
  Video and imaging circuitry only changes one way. Higher resolution, higher frame rates, and lower power requirements (particularly for UAV applications) equates to higher capacity and complexity. This is driving some software developers to sample the technique of offloading processor functions to run in parallel in field programmable gate arrays (FPGA).
  
  
• Sensor fusion enables sophisticated next-gen applications (Jun. 10, 2014)
  In this Product How-To article Rich Collins of Synopsys describes the importance of sensor fusion in connected embedded systems and how the company’s ARC EM4 32-bit CPU-based sensor IP Subsystem allows design of devices with the right performance/power consumption mix.
  
  
• Conquering the challenges of PCIe with NVMe in order to deliver highly competitive Enterprise PCIe SSD (Jun. 09, 2014)
  To help leading storage companies address the booming demand of PCI SSD (Solid State Drive), PLDA enhances the end-to-end data integrity functionality of its PCIe soft IP products and showcases a NVMe demo on its hardware.
  
  
• Low Power Analysis and Verification of Super Speed Inter-Chip (SSIC) IP (Jun. 02, 2014)
  In our current work, we focus on the low power analysis and verification challenges and the methodology used to verify low power design. The power-gating feature that we term Hibernation brings in significant power savings to Synopsys SSIC IP Controller. The verification tests the functionality of the Controller before, during and after hibernation state. The low power analysis will showcase the power savings achieved in SSIC IP with and Without Hibernation.
  
  
• Overcoming advanced SoC routing congestion with 2.5D system in packaging (May. 19, 2014)
  The use of a 2.5D system to integrate basic SoC functional blocks can eliminate much of the routing congestion that results when sending signals back and forth between cooperating elements.
  
  
• Performance optimization using smart memory controllers, Part 1 (May. 19, 2014)
  In this article, we explain how a smart memory controller can improve the performance of a system. We discuss various issues in an SoC and describe features of a smart memory controller that can be configured to mitigate these issues.
  
  
• Tradeoffs of LDO Architectures and the Advantages of Advanced Architecture "Capless" LDOs (May. 12, 2014)
  Power management of battery-powered electronic devices is becoming increasingly more important for the present and future microelectronics industry. This application note details the difference between low dropout (LDO) voltage regulators that use output capacitance and those that do not and how your system designs can benefit from or be improved by not using an output capacitor.
  
  
• An alternative to ADC, power and RF IC hardware: the S3 Group (May. 05, 2014)
  I was initially attracted to the levels of performance of a recently developed 12 bit SAR ADC (Part # S3ADS160M12BSM40LL) by the S3 Group. This small, very efficient, high-speed SAR ADC performs at 160 Msps at less than 31 fJ energy efficiency. I have been in the semiconductor industry for 26 years and this Energy Efficiency spec is new to me. I had never seen it on a datasheet.
  
  
• Auto Clock Generation in a SoC (May. 05, 2014)
  This paper discusses a novel idea on automatic clocks generation for a SoC. A standard configurable input file has all the required clock requirements in a SoC given by the designer. A scripting language is used to parse the input file. The script generates Synthesizable System Verilog RTL, System Verilog Assertions, Clock Constraints and Documentation in HTML format.
  
  
• Protecting multicore designs without compromising performance (Apr. 28, 2014)
  As data rates climb and malicious software attacks escalate, traditional approaches to security will be replaced by integrating such protection directly into the multicore-based Intelligent Packet Engine hardware IP.
  
  
• Adding CRC to BIST improves SoC safety & reliability (Apr. 28, 2014)
  Implementation guidelines for including CRC in SoC BIST controllers, automotive or otherwise.
  
  
• Behavioral Model of a DDR Memory Controller in a DFi - Frequency Ratio System (Apr. 21, 2014)
  The paper details the DDR MC Phase encoding algorithm in a DFi™ frequency ratio system. It is intended for a technical audience interested in learning about how the DDR MC encodes the PHY timing information in the Phase- Specific bus. Please refer to the DFi™ 3.1 specification for complete details on frequency ratio systems.
  
  
• Implementing a Design Management System (Apr. 17, 2014)
  I recently had lunch with a dejected engineer from a semiconductor startup in big trouble. After months of effort at no small expense, the chip design project was an utter failure, though not a result of the chip’s poor power, performance or area numbers. It was worse than that –– almost everything went wrong, from resource management, schedule slips and budget to feature creep and mismatched expectations.
  
  
• Scaling the 100 GbE Memory Wall (Apr. 14, 2014)
  All interrelated system-level tradeoffs, including performance, pin count, and area, ultimately are driven by power consumption considerations. At 100 and 400 GbE, network chip vendors must consider end-to-end solutions for equipment OEMs. To remain competitive, OEMs plan to introduce multi-terabit systems that aggregate multiple 100 Gbit/s ports on each line card.
  
  
• On-Chip Interconnect Costs Spawn Research (Mar. 27, 2014)
  With 16nm chips moving to production this year, companies are actively developing the 10nm and 7nm technology nodes. These generations are interconnect heavy -- more than 50% of their cost is due to the back-end-of-line (BEOL) wiring levels, and designs are dominated by interconnect delay.
  
  
• SoC interconnect architecture considerations (Mar. 25, 2014)
  The SoC interconnect architecture has a huge impact on what a given SoC can deliver. This is a huge topic of interest for the SoC designers. This is hardly surprising, with the SoC designs nowadays getting more and more communication-centric. Most of the SoCs nowadays consist of multiple processors, hardware accelerators for specific tasks, on chip memories, several standard interfaces to connect to real world devices and custom Intellectual Property (IP) blocks.
  
  
• Challenges associated with Digital-Analog combined IP's (Mar. 13, 2014)
  With the increase in complexity and the content of these Analog blocks, there is an enhanced focus to move more and more functionality, wherever possible, into the Digital domain which allows faster modifications, easy reuse and portability across technology nodes. Having said that there are inherent challenges associated with such Digital-Analog combined IP’s, referred to as Mixed Signal IP’s hereafter, both in Design and Verification in order to robustly signoff such IP’s at block verification level for integration in any SoC.
  
  
• Forward-Looking SoC-based PHY Architecture for Macro and Small Cell LTE eNode-Bs (Mar. 10, 2014)
  This paper describes an efficient, forward-looking architecture that enables handling of various form factors of LTE base stations with minimal software modification and without architecture changes. The architecture proposed allows easy migration to the next generation SoCs as well as to more powerful SoCs of the same generation. Our implementation of this architecture has now migrated two generations of SoCs for LTE Release 9 small and macro cells, and is ready for migration to a multi-sector, LTE-A macro base station.
  
  
• Understanding sigma delta ADCs: A non-mathematical approach (Mar. 06, 2014)
  In this paper, we will attempt to explain sigma delta converters with a non-mathematical approach, covering the basic concepts of noise shaping and oversampling, explained with the help of some examples. These concepts along with digital decimation filters are later incorporated together to reveal the magic behind sigma delta converters. This paper also covers the basics of first and second order sigma delta ADCs and how the order of the sigma delta modulator impacts the performance of the ADC.
  
  
• Smaller scale chip design relies on creative thinking and collaborative workflow (Mar. 05, 2014)
  Chip design can be a complex and time consuming endeavor that demands accuracy and speed. While larger enterprises have the wherewithal to invest in sophisticated EDA (electronic design automation) tools for development and verification, smaller research facilities within rapidly growing tech companies have to rely on a disciplined, integrated team approach to development.
  
  
• Scalable Architectures for Analog IP on Advanced Process Nodes (Mar. 03, 2014)
  This paper elaborates on how ADCs can work with Moore's Law to move with the power and area scaling trends that are common for digital circuits. It will compare the main ADC architectures and conclude that the Successive-Approximation Register (SAR) based ADC is very well positioned as the architecture of choice for medium- and high-speed ADCs in modern SoCs, especially in 28-nm processes and beyond. It will describe implementations of the SAR ADC architecture that reduce power consumption and area usage dramatically, enabling SoC designers to successfully integrate these analog components in their next SoCs.
  
  
• The hardware (and software) implications of endianness (Mar. 03, 2014)
  Today’s SoCs integrate many hardware IP blocks; designers need to be aware of the order of bytes on the byte lanes of connecting buses when transferring data. In a system with several discrete hardware components - such as a host processor and external devices connected to it via a PCI bus, for example - the hardware components may support different endianness modes. Device driver developers need to make the data transfers among these hardware components endianness-proof.
  
  
• Next Generation Wireless IP for the Internet of Things (Feb. 24, 2014)
  Most embedded systems today use some form of wireless connectivity. Specifically, the Internet of Things would not be possible without wireless interfaces. There are many considerations in the integration of wireless connectivity into the core system-on-chip around which systems are built. This paper provides a perspective on the integration of wireless connectivity subsystems within the system-on-chip (SoC).