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IP / SOC Products Articles

• RRAM: A New Approach to Embedded Memory (Feb. 11, 2014)
  The emergence of the Internet of Things (IoT) and the insatiable demand for smart devices in every aspect of life is driving a complete overhaul of traditional wisdom in the microcontroller and embedded memory markets.
  
  
• Design Tip: Implementing an SoC with dependable 50% duty cycles (Jan. 27, 2014)
  This article describes a new approach to implementing clock dividers in a system-on-chip design that supports both high performance and low power. It uses a dual edge counter-based configurable frequency divider that can not only divide the clock frequency for both even and odd configurable division factors, but at the same time maintains a 50% duty cycle of the output divided clock.
  
  
• PCIe and storage devices get connected (Jan. 20, 2014)
  SSDs (solid-state drives) are rapidly becoming the storage method of choice. With this changing of the guard from hard-disk drives to SSDs, there is a need for different connections than are used for hard drives or peripherals to utilize the an SSD's full potential. The connector and protocols discussed here are the future for the storage industry.
  
  
• Using USB 3.1's Multiple INs To Reach 10 Gbps Data Rates (Jan. 16, 2014)
  When working with USB 3.1, designers are challenged to provide the 10 Gbps USB 3.1 speeds that customers expect while supporting backward compatibility with USB 3.0 devices in a hub topology.Using multiple INs provides a greater level of flexibility to the system.
  
  
• Overcome memory-imposed access rate and bandwidth constraints (Jan. 13, 2014)
  Design teams building high-speed, next-generation network communications equipment suffer under the constraints imposed by memory. Some design solutions use only on-chip memory which is inherently limited in capacity and competes with silicon area that could be otherwise used for computation or other functionality. More complex applications require external memory and at the processing rates available today need the highest possible random access rate to that memory. Traditional memory interfaces are a burden to performance because they are plagued by slow speeds, lengthy latency, and high pin counts. As a result, conventional design approaches to implementing external memory have already reached the point of diminishing returns.
  
  
• Moving PCI Express to Mobile (M-PCIe) (Jan. 06, 2014)
  This paper will begin with a quick overview of the specification and its application space, and then go into details such as bandwidth and clocking considerations, PHY interface differences, power management impacts, and the tradeoffs related to choices around link-layer changes. These changes may impact the transaction and application layers of devices moving from PCIe to M-PCIe, and the paper will detail those issues. A basic understanding of PCI Express concepts is helpful but not required.
  
  
• Shaving power/area with merged logic in SoC designs (Jan. 02, 2014)
  In the modern era, there is always a requirement to achieve high frequency with lower power consumption. Achieving both targets simultaneously is very difficult and the situation becomes even more complex while moving down the technology nodes due to various sub-micron effects
  
  
• Optimizing Sensor Performance with 1T-OTP Trimming (Dec. 30, 2013)
  A sensor is a device that detects a change in a stimulus and converts it into an electronic signal that can be measured or recorded. The stimulus can be many things, including a physical property, environmental parameter, chemical composition or a location, to name just a few. All sensing elements have nonlinearities that include an intrinsic nonlinearity over sensing range along with offset and sensitivity nonlinearity variations over temperature.
  
  
• Portable and scalable solution for off-screen video frame composition and decomposition using OpenGL ES (Dec. 30, 2013)
  One of the most essential software components in multimedia applications like video communication, video networking, video security etc., is a video frame composition and decomposition module for off-screen surfaces. Off-screen surfaces are those video frames which are not displayed on the screen.
  
  
• The growing role of analog-digital on-chip integration in saving energy (Dec. 16, 2013)
  Mixed-signal silicon design, bringing the worlds of analog and digital technology onto a single die, has never been an easy task. Formerly, the analog and digital teams would work independently on their designs, leaving the place and route team with the thankless task of integrating everything onto a single chip. A microcontroller design, with all of its carefully thought out peripherals, would be routed leaving analog-sized holes for the oscillator, ADC and transceivers needed to complete the design.
  
  
• Mixed Signal Design & Verification Methodology for Complex SoCs (Dec. 16, 2013)
  This paper describes the design & verification methodology used on a recent large mixed signal System on a Chip (SoCs) which contained radio frequency (RF), analog, mixed-signal and digital blocks on one chip. We combine a top-down functional approach, based on early system-level modelling, with a bottom-up performance approach based on transistor level simulations, in an agile development methodology. We look at how real valued modelling, using the Verilog-AMS wire that carries a real value (wreal) data type, achieves shorter simulation times in large SoCs with high frequency RF sections, low bandwidth analogue base-band sections and appreciable digital functionality including filtering and calibration blocks.
  
  
• Why There's No Need to Fear JESD204B (Dec. 12, 2013)
  A new converter interface is steadily picking up steam and looks to become the protocol of choice for future converters. This new interface, JESD204, was originally rolled out several years ago, but it has undergone revisions that are making it a much more attractive and efficient converter interface.
  
  
• Understanding - and Reducing - Latency in Video Compression Systems (Dec. 02, 2013)
  In the video world, latency is the amount of time between the instant a frame is captured and the instant that frame is displayed. Low latency is a design goal for any system where there is real-time interaction with the video content, such as video conferencing or drone piloting. But the meaning of “low latency” can vary, and the methods for achieving low latency aren’t always obvious. Here we’ll define and explain the basics of video latency, and discuss how one of the biggest impacts in reducing latency comes from choosing the right video encoding.
  
  
• Development of a 4K 10-Bits HEVC Encoder (Nov. 25, 2013)
  The new High Efficiency Video Coding (HEVC) video compression standard results from the work of the latest joint project of the ISO/IEC Moving Picture Experts Group (MPEG) and ITU-T Video Coding Experts Group (VCEG) standardization groups, performed under the name of the Joint Collaborative Team on Video Coding (JCT-VC) (ITU-T and ISO/IEC).
  
  
• Optimizing High Performance CPUs, GPUs and DSPs? Use logic and memory IP - Part II (Nov. 21, 2013)
  In Part I of this two-article series we described how the combination of logic libraries and embedded memories within an EDA design flow can be used to optimize area in CPU, GPU or DSP cores. In Part II we explore methods by which logic libraries and embedded memories can be used to optimize performance and power consumption in these processor cores.
  
  
• The role of IP in the new generation of data center SoCs (Nov. 21, 2013)
  Exciting times are ahead for the next-generation of data center applications including network switches and compute servers. As ASSP suppliers implement a new class of SoCs supporting the latest SDN architectures and low-power micro servers, proven third-party IP will become necessary to help them quickly integrate the required functionality.
  
  
• An Introduction to Caskeid - Wireless Stream Synchronisation IP (Nov. 18, 2013)
  It’s a trend happening everywhere today: devices are going wireless and connecting to the Internet. And not just the ubiquitous smartphones, tablets and the smart TV either; add to this a growing list of consumer electronics products: refrigerators, ovens, games consoles, central heating systems, weather stations, radios and home stereo systems. Indeed the simple home stereo is struggling in the digital world. Countless inputs and control methods, incompatible interfaces, and way too many wires have created a home entertainment headache.
  
  
• Dealing with SoC metastability problems due to Reset Domain Crossing (Nov. 13, 2013)
  This article will review some of the conditions under which RDC occurs and propose some ways to deal with the problems that occur up front in the design phase.
  
  
• Display Driver with on-chip frame buffer and a scalable image compression engine (Nov. 11, 2013)
  A display Driver with on-chip frame buffer and a scalable image compression codec reaching visually lossless image quality is presented. The frame buffer compression codec can encode and decode up to eight pixels in one clock cycle. Integrating a whole frame buffer with RGB=888 or 10-10-10 bits into the display driver sharply reduces power dissipated between the AP chip and Display board. The existing working chips are manufactured by both UMC and TSMC 55nm high voltage CMOS process.
  
  
• How to specify and integrate successfully a measurement analog front-end including its power computation engine in an energy metering IC (Nov. 04, 2013)
  Based on the system specification of a typical smart meter, this article demonstrates the importance of carefully selecting the power metering IP solution so that its specification matches the standard requirements and copes with the application challenges. This article then pinpoints thoroughly the various issues that must be taken into account for the selection of the Silicon IP and helps identify the possible trade-offs between the performance of the Mixed-signal Front-end (MFE) and that of the Power and energy Computation Engine (PCE).
  
  
• Optimizing high-performance CPUs, GPUs and DSPs? Use logic and memory IP - Part I (Oct. 29, 2013)
  In this two-part article we describe available logic library and memory compiler IP and a typical EDA flow for hardening processor cores. Part I continues on to provide innovative techniques, using those logic libraries and memory compilers within the design flow, to optimize processor area.
  
  
• Meticom: Bridging FPGAs & MIPI-Enabled Devices (Oct. 23, 2013)
  Since MIPI as an interface was never intended to serve non-mobile applications, interfacing to FPGAs was never made a priority. This makes perfect sense, since the majority of FPGAs are not well-suited for use in high-volume mobile devices. On the other hand, FPGAs are quite common in medical, industrial, and automotive applications.
  
  
• Understanding - and Reducing - Latency in Video Compression Systems (Oct. 07, 2013)
  In the video world, latency is the amount of time between the instant a frame is captured and the instant that frame is displayed. Low latency is a design goal for any system where there is real-time interaction with the video content, such as video conferencing or drone piloting.
  
  
• Root Cause Analysis (RCA) of Soft Digital IP to improve IP Quality & Reusability (Oct. 07, 2013)
  
  
  
• Why using Single Root I/O Virtualization (SR-IOV) can help improve I/O performance and Reduce Costs (Oct. 07, 2013)
  In this paper, we will explore why designing systems that have been natively built on SR-IOV-enabled hardware may be the most cost-effective way to improve I/O performance and how to easily implement SR-IOV in PCIe devices.
  
  
• Verification challenges of ADC subsystem integration within an SoC (Oct. 01, 2013)
  An SoC designer is not required to know the deep design intricacies of any IP they are integrating into the SoC. So even from the perspective of an SoC designer, if the ADC is considered as a black box, there are many factors that decide the quality of performance of the ADC at the SoC level. We must take care of these factors.
  
  
• Using Sidense 1T-OTP in Power-Sensitive Applications (Sep. 30, 2013)
  There are alternatives to putting an OTP on-chip. The data can be held off-chip in some sort of programmable memory (or, perhaps, ROM). But this obviously has the disadvantage of requiring the cost of an extra chip. In smartphones it is not just the cost of another chip that is a problem, but the additional volume taken up by two chips. There is just not a lot of room inside a smartphone to fit everything.
  
  
• How Reusable IP Helps Reduce Product Design Cycles (Sep. 25, 2013)
  Reusing IP for product development has long been considered a promising option to deliver on most of these factors. In this column, we extend the concept of reusable IP to system design.
  
  
• Data acquisition systems and SoCs - A guide (Aug. 28, 2013)
  Data acquisition systems (abbreviated with the acronym DAS or DAQ) measure real world signals (temperature, pressure, humidity etc.) by performing appropriate signal conditioning on a raw signal (amplification, level shifting, etc.), and then digitizing and storing these signals.
  
  
• Building high performance interrupt responses into an embedded SoC design (Aug. 26, 2013)
  Executing interrupt service routines using conventional techniques requires many clock cycles and limits the ability of the designer to verify the SoC IP (intellectual property) during silicon testing. Here is a technique to make that easier.