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IP / SOC Products Articles

• Designing a next-generation video interface with thunderbolt technology (Aug. 19, 2013)
  The traditional method for handling video data uses a USB interface for data and DisplayPort or HDMI for video output. With the introduction of the Thunderbolt interface, a system interface can be simplified with one connector for both data and video.
  
  
• Optimized Memory Accessing Through Coupling of Byte Enable Signals (Aug. 19, 2013)
  A comparison between the conventional memory access algorithm and the optimized algorithm for three different interfaces (Memory/ AHB/ IPS) is depicted below.
  
  
• Deriving design margins for successful timing closure (Aug. 15, 2013)
  SOC design timing performance degrades at every implementation step towards working silicon, so it is very important to have a right estimate of design frequency starting at the first stage of design implementation. Design margins make this possible.
  
  
• NVM memory: A Critical Design Consideration for IoT Applications (Aug. 12, 2013)
  The explosion of information that IoT devices will gather will require huge numbers of processors to process and manage the data from these IoT devices along with lots of low-cost, secure and reliable embedded non-volatile memory (NVM) for code storage, sensor trimming, device configuration, security keys and other storage functions. Virtually every one of the projected billions of IoT devices can use some amount of one-time programmable (OTP) memory.
  
  
• Design planning for large SoC implemention at 40nm - Part 3 (Aug. 12, 2013)
  A thorough exercise during physical architecture is the foundation for an efficient floorplan. It helps in reducing the overall turnaround time of the physical design phase. The broader prospective of the floorplan should be performed during the physical architecture phase, and the actual floorplaning phase should address the finer details of the floorplan, which impacts the physical design’s QoR.
  
  
• Free the Gadgets "Wireless Charging" (Aug. 12, 2013)
  Scientists are working on to develop methods to transmit power wirelessly that could cut the clutter and the hassle for carrying so many add-ons to a device. It may sound futuristic but not unrealistic.
  
  
• Design and Implementation of SD Host Controller IP Core (Jul. 29, 2013)
  This paper discusses a method to design an SD Host Controller IP Core that can be implemented on FPGAs. FPGAs are being widely deployed in various applications including industrial, commercial and military applications. Secure Digital is the most widely used portable memory standard. Its ultra-compact and rugged architecture, simple interface, high security, low power consumption, reliable operation and interoperability have made it the de-facto solution for portable storage. The IP Core is designed in accordance with SD Host Controller Specification 3.0 and implements many advanced features. The IP Core is developed, implemented and tested and the performance obtained matches industry standards.
  
  
• Navigating successful USB 3.0 compliance (Jul. 16, 2013)
  In this article, we explore important advanced preparations necessary to achieve USB compliance along with several key elements necessary to achieve prompt and effective USB 3.0 time-to-market.
  
  
• Design planning for large SoC implementation at 40nm - Part 2 (Jul. 15, 2013)
  Die size and power estimations are at the foundation of SoC implementation. The key is how early and how accurately can it be done. These two parameters are the main data point for making some critical decisions early on. Freezing the die size in the early phase of SoC development gives a solid foundation for the physical designer, but it is a challenge to come up with an optimum and realistic estimation.
  
  
• Silicon Intellectual Property - Delivering value to customers (Jul. 08, 2013)
  With many IP vendors in the market, the question is what really adds value to customers and help them choose the right vendor. How can an IP centric focus with services built around IPs can deliver value to customers?
  
  
• System Design in the Real World (Jul. 04, 2013)
  Debate rages over the correct methodology for SoC-based system design. Is it the traditional register transfer level (RTL) flow? Or is it high-level synthesis of a C-language behavioral model? What about an intellectual-property (IP) reuse methodology that minimizes any kind of code generation? Every expert has an opinion of how design teams ought to move from requirements definition to manufacturing.
  
  
• Understanding in-loop filtering in the HEVC video standard (Jun. 25, 2013)
  High Efficiency Video Coding (HEVC) is a video compression standard, a successor to H.264/MPEG-4 AVC (Advanced Video Coding), jointly developed by the ISO/IEC Moving Picture Experts Group (MPEG) and ITU-T Video Coding Experts Group (VCEG) as ISO/IEC 23008-2 MPEG-H Part 2 and ITU-T H.265.
  
  
• Link synchronization and alignment in JESD204B: Understanding control characters (Jun. 24, 2013)
  The transition to JESD204B as the digital interface of choice for high speed data converters is well underway. The JESD204 interface was released in its original form, JESD204, in 2006 revised to JESD204A in 2008, and in August 20011 revised once more to the current JESD204B.
  
  
• The Fundamentals of a SHA-256 Master/Slave Authentication System (Jun. 20, 2013)
  For more than 10 years, SHA-1 authentication has been used to effectively protect intellectual property from counterfeiting and illegal copying. As computer technology advances, customers are asking for an even higher level of security.
  
  
• DDR3: A comparative study (Jun. 20, 2013)
  This paper introduces the concept of DDR (Double Data Rate) memories and briefly delineates the features and functionalities of DDR3 memories in contrast with those of DDR2 memories, along with some basic guidelines to create an efficient DDR3 memory controller.
  
  
• Low Power Design for Testability (Jun. 17, 2013)
  Design for testability (DFT) and low power issues are very much related with each other. In this paper power reduction methodologies are discussed for a given design. Power management circuitries are developed to reduce functional power of the design. Power aware Scan Chains are implemented to create test environment which result into reduction in test power. Design for testability is applied to test power management circuits using Power Test Access Mechanism. Also few methods are discussed to implement DFT to test power management circuitry and improve test and fault coverage during ATPG.
  
  
• Scaling NAND flash to 20-nm node and beyond (Jun. 11, 2013)
  Intel-Micron have recently introduced a scalable planar NAND cell for the 20nm technology [1]. Replacement of conventional wrap floating gate (FG) NAND memory cell with a High-K/Metal gate planar cell that can scale to the 20nm node and beyond was a significant challenge and required comprehensive material and cell exploration and optimization. This paper discusses some of the fundamental cell design issues considered and addressed to arrive at this planar cell technology including the reasoning behind choosing the planar floating gate cell over the nano-crystal cell, and the nitride cell.
  
  
• Using non-volatile memory IP in system on chip designs (Jun. 11, 2013)
  While unlimited re-programmability might be seen as an advantage during software development, once the device is shipped it becomes a product’s greatest vulnerability...
  
  
• Soft memories in PD flow : Myth and Reality (May. 28, 2013)
  Even though soft memories or fifos make life easy for the rtl designer it may create issues in different stages of the PD flow under specific circumstances. We will discuss these issues in detail and we will see how this can be handled at the PD end.
  
  
• How to use ECC to protect embedded memories (May. 27, 2013)
  In this article we discuss transient error detection and correction methods using advanced error correction code (ECC) based solutions for embedded memories in order to meet the requirements of today’s high-reliability applications.
  
  
• Address jitter and noise more effectively with DDR4, part1 (May. 22, 2013)
  The latest generation of DDR memory, DDR4, doubles the speed of the current generation of DRAMs, DDR3, with end-of-life data rates of 3.2 GT/s. Compared to the first generation of DDR memory, which started out at 200 MT/s, DDR4 will be running almost 16 times faster.
  
  
• Generic DDR Behavioural Model (May. 20, 2013)
  This paper represents a generic executable architecture. It represents the efficient behaviour of the Memory Model to be used for verification of SOC communicating with DDR SDRAMs or can be used as the third party Model verification (passive element). Paper shows the capability as standalone VIP architecture and also represents the market value of DDR model in the present technical era with different technical views and challenges faced. It also givessolution of supporting different part number of established DDR vendors like Micron, Elpida, Samsung etc.
  
  
• Design planning for large SoC implementation at 40nm: Guaranteeing predictable schedule and first-pass silicon success (May. 20, 2013)
  Modern SoC development requires a holistic approach and thorough planning starting at the design architecture of the SoC. The ASIC implementation process has to keep pace with the design complexity, performance, and time-to-market, all while ensuring first-time silicon success.
  
  
• How small vendors compete in analog IC market (May. 02, 2013)
  Can a small fabless analog vendor compete with the top five analog IC vendors in global markets? This question is being asked often, especially in the context of emerging Chinese end-system OEMs. Europe used to have many small analog IC specialists – most but not all have by now been acquired. In this case study, we will compare one such small but well-established company competing with the world’s largest analog company.
  
  
• Intellectual property security: A challenge for embedded systems developers (Apr. 29, 2013)
  A company’s success - and its future - depends on the creation and successful defense of intellectual property (IP), which is generally defined as "creations of the mind for which exclusive rights are recognized.” IP is the outcome of innovation and work done by an organization/person and gives a company's products an edge over competitors.
  
  
• Using audio codecs IP as the digital audio hub in mobile multimedia systems (Apr. 24, 2013)
  By integrating an audio analog codec that implements the 'audio hub' functionality and is able to process and mix audio signals from asynchronous sources, system designers can free the scarce main processor resources for more relevant tasks and simplify the system design, thus achieving a more effective solution.
  
  
• A Low Complexity Parallel Architecture of Turbo Decoder Based on QPP Interleaver for 3GPP-LTE/LTE-A (Apr. 22, 2013)
  This paper propose an improved method called the modified warm-up-free parallel window(PW) MAP decoding schemes to implement highly-parallel Turbo decoder architecture based on the QPP(Quadratic Polynomial Permutation) interleaver of 3GPP LTE/LTE-A standards.
  
  
• Demystifying the PLL (Apr. 02, 2013)
  When designing a digital communications system on a mixed-signal chip, digital designers tend to avoid PLLs because of their inherent analog nature, and analog designers stay away from them because IDEs involve coding. This article presents a different way of designing a simple PLL.
  
  
• How a MicroBlaze can peaceably coexist with the Zynq SoC (Mar. 28, 2013)
  The Xilinx Zynq-7000 All Programmable SoC already has plenty of processing power onboard. But the presence of powerful twin Cortex-A9 processors and associated peripherals in Zynq's application processing unit (APU) should not keep you from adding one or more MicroBlaze processors in the same package, if your application would benefit from them.
  
  
• Introduction to OpenVG for embedded 2D graphics applications (Mar. 28, 2013)
  OpenVG is an API designed for hardware-accelerated 2D vector graphics. It was designed to help manufacturers create more attractive user interfaces by offloading computationally intensive graphics processing from the CPU onto a GPU to save energy.