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IP / SOC Products Articles

• Using parallel FFT for multi-gigahertz FPGA signal processing (Mar. 28, 2013)
  High-speed fast Fourier transform (FFT) cores are an essential requirement for any real-time spectral-monitoring system. As the demand for monitoring bandwidth grows in pace with the proliferation of wireless devices in different parts of the spectrum, these systems must convert time-domain to frequency-domain ever more rapidly, necessitating faster FFT operations.
  
  
• Communication centric test and debug infrastructure for multi core SoC (Mar. 25, 2013)
  A communication centric SoC debug approach using control transactions, as an extension of the traditional, processor based debug access and control is presented in this paper. A structured approach is presented to control both the processor core and other critical hardware units in a hardware synchronized manner, thereby enabling both synchronous stop and start during a debug session. An efficient and processor independent mechanism to have explicit control the system at run time is presented.
  
  
• Share with PCI Express (Mar. 25, 2013)
  As kids we were taught that sharing is good. The semiconductor industry seems to have forgotten the spirit of that lesson, but one technology that reminds us of what our parents taught us is PCI Express (PCIe).
  
  
• How FPGAs are breathing new life into the analog video format (Mar. 21, 2013)
  Digital video broadcasting, video compression, and ever expanding video resolutions such as 4k x 2k dominate the news in electronics magazines. Yet that little yellow RCA connector remains ubiquitous and large numbers of people still rely on NTSC or PAL analog broadcasting for their viewing pleasure. This article looks at how FPGAs are breathing new life into this presumed dead format.
  
  
• Why migrate to DDR4? (Mar. 13, 2013)
  A knowledge gap exists between the presentation of the technical details in JESD79-4 and understanding the underlying motivations and rationale that led to the standard. In an attempt to bridge that knowledge gap, let’s explain some of the purpose of the DDR4 SDRAM device, and frame it in the context of system level trends.[
  
  
• Design Transition from Sync to Async: Design and Verification Challenges (Mar. 11, 2013)
  This article deals with various challenges faced in modifying a synchronous design to an asynchronous one. It aims to provide a brief overview of design and verification aspects to consider while making this transition.
  
  
• Optimizing clock tree distribution in SoCs with multiple clock sinks (Mar. 11, 2013)
  In this article we describe a structure and a method for propagating clock signals to a multiplicity of clock sink nets in a system-on-chip (SoC) design. We include an improved buffering and wiring apparatus that allows reduction of the number of clock stages, the overall latency, the clock skew, and uncertainty.
  
  
• Building a security-optimized embedded design using protected key storage (Mar. 08, 2013)
  In this Product How-To article, Todd Whitford and Kerry Maletsky of Atmel Corporation describe the many ways in which the security of an embedded microcontroller design can be compromised and how to use the company’s ATSHA204 authentication device to protect critical system IP.
  
  
• "So, when will you be done with your design?" (Mar. 07, 2013)
  Not exactly the question a typical design engineer is looking forward to. You’re at the start of a new project and it is time to commit to a development schedule. Now what? Your first instinct is to be vague. Use verbs like “should” and “hope” and lots of conditional statements. But you know that’s not going to fly. You can give your best estimate. But you’re usually too optimistic and then you will get yelled at when you don’t meet that commitment.
  
  
• Long live the battery! (Mar. 04, 2013)
  There are many factors that affect the device’s power efficiency, which can be expressed in the number of hours between battery charges. Today, in the era of HD mobile screens there are two major issues that contribute to high battery drain – display brightness and power dissipation in the video and graphics subsystem. In this paper we will discuss the latter one – smart video and display pipeline in the System-on-Chip. Smart, which means providing similar performance to competitive solutions, but requiring much less power.
  
  
• Understand and perform testing for MIPI M-PHY compliance (Feb. 19, 2013)
  As MIPI Alliance standards gain increasing acceptance in the world of mobile device design, engineers need to become proficient at electrical PHY layer compliance testing for the higher speed M-PHY serial interconnects. A full set of tests spanning both the transmitter and the receiver are required to validate designs – a task that is made tougher as speeds and complexity increase. Understanding how to setup and perform critical verification and debug tests is critical to any successful M-PHY development effort.
  
  
• Designing low-power video image stabilization IP for FPGAs (Feb. 19, 2013)
  Image stabilization is an important capability for many electro-optic sensors, where an operator or user is required to view the output imagery. The technique can therefore enhance many practical viewing systems, spanning a very broad range of applications including those found in defense and security sectors.
  
  
• Silicon-Accurate Fractional-N PLL Design (Feb. 18, 2013)
  Fractional-N PLLs are a useful class of PLLs and not well understood. This paper explains in simple terms how these differ from a regular integer PLL. Common applications are listed along with a brief description of the key performance parameter – jitter.
  
  
• Who's managing your power management? (Feb. 12, 2013)
  Today’s complex systems employ a wide variety of semiconductor technologies. From the deepest sub-nanometer processors to the analog I/O, it’s easy to see the need for power management devices for multiple voltages – 1.0V, 1.2V, 1.5V, 1.8V, 2.2V, 2.5V, 2.8V, 3.0V, 3.3V and more – all in the same box.
  
  
• Implementing analog functions in rugged, rad-hard FPGAs (Feb. 12, 2013)
  FPGAs have already changed the cost/reliability paradigm for embedded systems in high-reliability applications, thanks to advances in hardness and power reduction. But on many embedded applications for high-reliability markets, designers depend on a number of peripheral analog components such as analog-to-digital and digital-to-analog converters to talk to the real world.
  
  
• General Partitioning Guidelines for Validation of Large ASIC Designs On FPGA (Feb. 11, 2013)
  Today's FPGAs have the capability to contain a complex and large system-level design. However, in some cases, there is a requirement for these designs to be partitioned among several FPGAs for validation or prototyping. But, splitting the design into several FPGAs can create various partitioning issues, especially for relatively large designs with complex connectivity. These issues could possibly be circumvented if certain guidelines are followed. This paper talks about the general partitioning challenges and the guidelines that can be followed to get past these issues
  
  
• Open-source hardware for embedded security (Feb. 05, 2013)
  Imagine you’re waiting in line, queuing to enter a major event. The ticket you have bought online is stored on your smart phone. As you swipe your phone over some designated area, an NFC connection is set up, your ticket is validated and the gates open to let you in. And the good thing is, that it all happened anonymously.
  
  
• Reap the benefits of a general-purpose interface USB 3.0 device controller (Jan. 23, 2013)
  Since its introduction in 2000, USB 2.0 has been the de-facto interface standard of the PC world. With a transfer rate of 480Mbps, it is lightning fast and served as an apt solution for many interfacing needs. However, with the rise in demand for higher data rate applications like HD video streaming and high capacity hard disks, the reign of USB 2.0 is slowly being replaced by its successor – USB 3.0.
  
  
• Using SoCs for portable medical equipment (Jan. 22, 2013)
  Portable medical electronics has seen tremendous growth and adoption in the recent years. More equipment variants are being introduced in the market by an increasing number of companies. The need of the hour is better mass producible designs which are low in complexity and provide acceptable performance so as to keep the cost of the device low. To achieve this, designers need to consider power efficiency, cost, form factor, and FDA certification of components, among other factors.
  
  
• Integrating large-capacity memory in advanced-node SoCs (Jan. 15, 2013)
  In today’s system-on-chip (SoC) designs, memory content can consume over 50% of chip area. In addition, the size of individual memories has grown to approximately 40 Mb of contiguous memory. This combined increase can significantly impact the overall power, performance, and area of the chip, as well as manufacturing yield. Successful integration of large-capacity memory in advanced-node SoCs requires the right approach.
  
  
• Four soft-core processors for embedded systems (Jan. 09, 2013)
  Since 2000, the folks at Realtime Embedded have concentrated on helping companies develop embedded systems used in advanced products. Their four primary focus areas are FPGA, Linux, virtual hardware, and multicore processing systems. Realtime Embedded is involved in customer and financed research projects, in house and on site, spanning a wide range of industries.
  
  
• The Case for Developing Custom Analog (Jan. 07, 2013)
  Increasingly, product managers are considering a custom Analog SoC as an effective way to drastically reduce BOM costs. What would have been considered a radical product innovation just a few years ago, is now viewed as a viable route as even where product volumes are considered low NRE costs can in fact be recovered in short period of time. Innovative SoC solutions are challenging but the benefits are compelling where risk can be mitigated by choosing a development partner with a clear understanding of all the system components and of the various technology options for the SoC implementation. In a recently issued paper, S3 Group’s experts talk about the advantages of custom SoCs and build a strong business case for investment in a SoC development.
  
  
• The Past, Present and Future of DDR4 Memory Interfaces (Dec. 14, 2012)
  The latest DDR4 SDRAM memory standard offers significant performance benefits for SoC designers. Graham Allan, senior product marketing manager for DDR at Synopsys, discusses some of the challenges that design teams face in making the change from DDR3.
  
  
• Vertical crosspoint memory supports ultra-low-power devices for Internet of Things (Dec. 14, 2012)
  With its widely varied smart devices, the Internet of Things (IoT) is creating a demand for microcontrollers made application specific by software instead of dedicated system on chip (SoC) designs.
  
  
• Introduction to USB -- Part III (Dec. 13, 2012)
  USB can connect a series of devices using a tiered star topology. The key elements in USB topology are the host, hubs, and devices.
  
  
• A Performance Architecture Exploration and Analysis Platform for Memory Sub-systems (Dec. 10, 2012)
  In this paper, we outline the various parameters that affect the memory sub-system performance and also introduce the Sensitivity Analysis and Feature Exploration methodologies to analyze the degree of impact of each of these parameters. This platform, when used at an early architectural exploration phase, provides valuable feedback to the memory device, controller and PHY architects to focus on optimizing the most critical parameters. We present a case-study to analyze a next generation mobile DRAM based memory sub-system using our proposed performance architectural exploration platform, and provide a ranking metric for all the parameters that affect the memory sub-system performance for key mobile applications.
  
  
• Debunking myths about analog IP at 28 nm (Dec. 04, 2012)
  The economics of system-on-chip development are objective and well understood. Industry-wide trends set the stage for integrating more functions into a SoC, which then drives the scaling down of process technology nodes. In the resulting product, all of the previous product’s functionality is implemented while more functional blocks are added to build increasingly complex functionality. This trend is not questioned - it is an axiom.
  
  
• Achieving maximum motor efficiency using dual core ARM SoC FPGAs (Dec. 03, 2012)
  Michael Parker of Altera Corp. describes how to use an ARM/FPGA-based SoC for real-time machine control algorithm operations. He also describes how the SoC can function as a network processor to link up to the real-time network protocols used in many industrial automation applications.
  
  
• Choosing serial interfaces for high speed ADCs in medical apps (Nov. 30, 2012)
  In medical applications such as MRI, ultrasound, CT scanners, and digital X-ray, high channel count analog-to-digital converters (ADCs) are used to sample large arrays of data.
  
  
• NVMe powers SSDs in the enterprise (Nov. 28, 2012)
  With the emergence of non-volatile memory express (NVMe), a scalable host controller interface specifically developed for PCIe SSDs, and a supporting ecosystem plus dedicated devices such as NVMe programmable flash controller chips, the potential of PCIe SSDs for enterprise computing applications can be fully realized.