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IP / SOC Products Articles

• Universal Flash Storage: Mobilize Your Data (Nov. 26, 2012)
  Universal Flash Storage (UFS) was created for mobile applications and computer systems requiring high performance and low power consumption. These systems typically use embedded Flash based on the JEDEC standard eMMC. UFS was defined by JEDEC as the evolutionary replacement for eMMC offering significantly higher memory bandwidth. The standard builds on existing standards such as the SCSI command set, the MIPI Alliance M-PHY and UniProSM as well as eMMC form factors to simplify adoption and development.
  
  
• Maximizing battery life on embedded platforms - Part 4. Turning off peripherals and subsystems (Nov. 20, 2012)
  Some systems have very clever peripherals and they are not just there to fill up the available silicon space. So, use the peripheral system to your advantage. If you have a DMA engine and need to copy large amounts of data about then use it! You can either have the CPU go off and do something else in parallel during the transfer time or, if nothing else needs doing, put it to sleep and wake it up when the data is in place.
  
  
• Introduction to USB - Part I (Nov. 15, 2012)
  This chapter presents a quick introduction to USB. The first section in this chapter introduces the basic concepts of the USB specification Revision 2.0. The second section explores the data flow model. The third section gives details about the device operation. Lastly, the fourth section describes USB device logical organization. The full protocol is described extensively in the USB Specification Revision 2.0.
  
  
• Predicting PLL reference spur levels due to leakage current (Nov. 12, 2012)
  A simple model can be used to accurately predict the level of reference spurs due to charge pump and/or op-amp leakage current in a phased-locked loop system. Knowing how to predict these levels helps pick loop parameters wisely during the early stages of a PLL system design.
  
  
• JESD204B vs. Serial LVDS I/F for wideband data converter apps (Nov. 07, 2012)
  The JESD204A/B interface reduces the number of digital inputs/outputs between data converters and other devices, such as FPGAs and SoCs.
  
  
• Secure Mobile Payments - Protecting display data in TrustZone-enabled SoCs with the Evatronix PANTA Family of Display Processors (Nov. 05, 2012)
  Secure System-on-Chips (SoCs) based on ARM® TrustZone® technology enable both hardware and software components to be isolated as a secure subsystem within a complex SoC and as such focus on processing protected, sensitive and valuable assets, such as payment credentials, whenever these might be endangered with an attack, modification or capture. At the same time the main system software may be an open Rich OS platform that enables downloading and use of arbitrary third-party and non-trusted applications which can gain access to almost all system hardware elements.
  
  
• Driver Solutions for LED Backlighting (Oct. 30, 2012)
  White LEDs (WLED) are increasingly becoming the light source of choice for backlighting applications due to their attractiveness in power efficiency and form factor. This white paper looks into the design specifications and constraints for an LED driver for backlighting solutions. Architectural methods would be discussed to address these constraints.
  
  
• Memory solution addressing power and security problems in embedded designs (Oct. 22, 2012)
  Wireless monitoring devices and digital wallets are creating a new category of battery-powered system on chip (SoC) designs. This article will examine the memory requirements—static RAM (SRAM), read only (ROM), and non-volatile memory (NVM)—of these SoCs and offer an innovative solution to accommodate the new constraints of this category of design.
  
  
• Auto apps accelerated by triple-play graphics cores (Oct. 22, 2012)
  This article briefly introduces the i.MX6 family of processing devices from Freescale. In particular, we consider the Triple-Play graphics processing units (GPUs) featured in the i.MX6 devices and explains the advantages that result from using three specialized graphics engines. Also introduced are two companies that create human machine interfaces (HMIs) for automobiles using the i.MX6 hardware platform.
  
  
• Stretching the Dynamic Range of ADCs - A case study (Oct. 09, 2012)
  Whether your application is focused on wireless communications or instrumentation, the performance bottleneck is often the dynamic range of the analog-to-digital converter (ADC). Dynamic range is often a key parameter within signal processing systems and a shortfall can limit the quality and range of signals that can be received.
  
  
• System-on-chip technology comes of age (Oct. 08, 2012)
  This article describes the emerging importance of the SoC, its likely technological evolution and its potential impact on the semiconductor industry in a mobility driven age.
  
  
• The Challenges of USB 3.0 (Oct. 02, 2012)
  After a three-year teething period, USB 3.0 is finally mainstream. Microsoft and Apple support USB 3.0 in their latest releases of Windows and Mac OS X, respectively; Intel and AMD support USB 3.0 in their latest chipsets. This creates critical mass, which will cause USB 3.0 peripheral deployment to ramp significantly in the coming year.
  
  
• Pipeline AES S-box Implementation Starting with Substitution Table (Oct. 01, 2012)
  This paper is focusing on the most time consuming step of the AES algorithm. This step is a Non-Linear Byte Substitution that transforms some byte value into a new byte value through the use of an S-box Substitution Table. This table contains pre-computed inverted values for each of the 256 8-bit numbers (bytes) considered as elements of the Galois finite field GF(28).
  
  
• DRAM Controllers for System Designers (Sep. 24, 2012)
  Buried somewhere inside the system-on-a-chip (SoC) at the heart of your system is a DRAM controller—or maybe there are two, or four. They are carefully-crafted, tiny blocks of logic that quietly go about their business of connecting the internals of the SoC to external DRAM, requiring no attention from system designers. Or, they wreak havoc, wasting bandwidth, burning energy needlessly, and even allowing data to be corrupted.
  
  
• Viewpoint -- USB 3.0: Not just for wired apps (Sep. 24, 2012)
  The need to deliver faster, power efficient data transfers on every device is more evident than ever. NetGear, for example, recently demonstrated a commercially available Wi-Fi-AC router and adapter running at 1.2 gigabits per second (Gbps). Given that consumers want to move terabytes of video and photos through their homes and into the cloud., minimizing power consumption is the No. 1 design challenge.
  
  
• Configurable dividers for SOC / block-level clocking (Sep. 04, 2012)
  This article illustrates various implementations of configurable clock divider logic used in SOCs today and highlights their challenges, advantages or limitations over the others.
  
  
• Physical Attacks against Cryptographic Implementations (Sep. 04, 2012)
  Since the advent of side channel attacks, classical cryptanalysis is no longer sufficient to ensure the security of cryptographic algorithms. In practice, the implementation of algorithms on electronic devices is a potential source of leakage that an attacker can use to completely break a system. The injection of faults during the execution of cryptographic algorithm is considered as an intrusive side channel method because secret information may leak from malicious modifications of the device's behavior.
  
  
• Performance is marred by memory (Aug. 31, 2012)
  For many years the industry created faster and faster processors. This was possible because more transistors were available in each technology node that could be used to produce even more complex and optimized pipelines.
  
  
• Proposal of a Dynamically Reconfigurable Processor Architecture with Multi-Accelerator (Aug. 20, 2012)
  In this paper, we propose a dynamically reconfigurable processor architecture with a multi-accelerator using Dynamic Partial Reconfiguration (DPR) technology by XILINX. The proposed architecture consists of a processor, some memories, some buses, controllers and some dynamically reconfigurable accelerators. We employ a multi-bus system and design the controllers for a dynamically reconfiguration. A JPEG encoder and decoder that are open-source IPs are used as target applications. The proposed architecture is implemented on a Virtex-6 FPGA and evaluated regarding the circuit size and reconfiguration time. The results showed that the partial reconfiguration time was small enough.
  
  
• Growing audio requirements in SoCs (Aug. 08, 2012)
  As consumer devices such as tablets, media players and home theater systems continue to incorporate more audio functionality, the systems on chip (SoCs) designed for these devices become more complex. These SoCs must support a growing list of audio requirements such as a wider range of high-definition audio compression formats, multi-channel audio content, higher sampling rates and advanced audio post-processing functions.
  
  
• ASIC Implementation of a Speech Detector IP-Core for Real-Time Speaker Verification (Jul. 23, 2012)
  For voice processing it is important to ensure that the signal to be analyzed actually contains relevant information, especially if the system is operating in a real-time. This paper presents an IPcore speech detector for real-time systems, focusing on identification of segments of silence or voice, used in pre-processing of input signals to Speaker Recognition and Verification Systems. The IP-core was designed to be able to be adapted to different environments of use and based on energy of samples to classify them as voice or silence.
  
  
• OEM Custom Solutions - BOM Cost Reduction (Jul. 23, 2012)
  As process technology nodes advance, falling costs & increasing capacity on older nodes enable OEMs embark on custom ASIC developments to take advantage of higher levels of integration thereby realizing significant BOM savings. Never before have mixed signal ASIC developments been within reach of so many, lower volume applications. Choosing the right partner to realize the silicon development, in a cost effective and low risk manner, is still a challenge to be overcome by OEMs.
  
  
• Using code-coverage analysis to verify 2D graphic engines in automotive apps (Jul. 23, 2012)
  High-resolution graphics displays are becoming a key part of automotive manufacturers' strategies to simultaneously differentiate from their competitors, reduce production cost, and increase customer satisfaction. Our group at Fujitsu develops IP blocks and SoCs to help customers realize these advantages.
  
  
• FRAMs as alternatives to flash memory in embedded designs (Jul. 19, 2012)
  In recent years, integrated circuit manufacturers have been considering FRAM as a strong contender for embedded, non-volatile memory, as an alternative to flash technology. This article discusses key technology attributes of FRAM while exploring specific use cases that demonstrate FRAM’s advantages.
  
  
• Design of a 8051 Microcontroller in FPGA with reconfigurable instruction set (Jul. 16, 2012)
  This paper describes the design and implementation of a version of the 8051 microcontroller, one of the most commercially used microcontrollers in FPGA with reconfigurable instruction set.
  
  
• Revisiting the analogue video decoder: Brushing up on your comb filters (Jul. 12, 2012)
  With such a large number of video decoders in the market it might seem an unnecessary indulgence to spend time looking again at the design of this fundamental but apparently obsolete building block, and certainly new designs are not appearing on the market and haven't done so for three or four years.
  
  
• PCIe goes Clockless -- Achieving independent spread-spectrum clocking without SSC isolation (Jul. 09, 2012)
  PCI Express (PCIe) has established itself as the IO interconnect of choice for communication within the server and PC environment. Today, an emerging trend among designers is extending PCIe beyond the PC/server while maintaining the advantages of simplicity, bandwidth, scalability, low power and cost. One of the major system-level challenges in extending PCIe outside the box has been clock distribution between separated domains.
  
  
• Anti-fuse memory provides robust, secure NVM option (Jul. 06, 2012)
  Embedded non-volatile memory (NVM) intellectual property (IP) is a requirement for storing data that must be preserved when power to the chip is removed. NVM is found in almost every system on chip (SoC) design today, especially those targeting connected devices accessing content protected by digital rights management and sensitive financial or personal data. As these SoC designs migrate toward 28 nm and lower processes, engineering teams are re-examining the available commercial options. This reappraisal is occurring because of challenges presented by these smaller geometry processes. Suddenly, what was once an insignificant commodity is threatening to become a technology bottleneck.
  
  
• Understanding DDR SDRAM timing parameters (Jun. 26, 2012)
  Many engineers who have ever dealt with DDR SDRAM must have been intrigued by the various timing parameters of the DRAM. This article explains the various timing parameters and its impact on the performance of the DRAM.
  
  
• Sensor Interface - Analogue Front End Family "From the Real World to the Digital Word" (Jun. 25, 2012)
  Systemcom Ltd. launched the family of chip solutions which can be used for instance with light sensor, to capture light, then to process the information and provide data to the standard controlling unit (electronic device). The product line consists of silicon proven, so called IP ("Intellectual Property") modules, as the components of the sensor interface - Analogue Front End (AFE) family. It can be really said that such chip solutions make connection from the real world to the digital word.