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IP / SOC Products Articles

• Debunking 10GBase-T Myths (Jun. 11, 2012)
  While it may be true that good things come to those who wait, too much waiting can lead to uncertainty. Take 10GBase-T networking products, for example. The 10GBase-T standard published almost six years ago and the long wait for network gear has provided fodder for the digital rumor mill to churn.
  
  
• Smart SoCs drive 3G-to-4G transition (Jun. 05, 2012)
  The solution for delivering today’s escalating broadband mobile network traffic is to deploy many more basestations, closer to the user. To accomplish this, the Long-Term Evolution (LTE) standard includes the concept of the multiradio-access-technology heterogeneous network (multi-RAT HetNet), which combines big, traditional basestations with small cells.
  
  
• Data-in-transit Protection for Application Processors (Jun. 04, 2012)
  This whitepaper attempts to help designers tasked with building an Application Processor based system that needs to incorporate support for what is typically called 'Data in Transit Protection'.
  
  
• Designing embedded SoCs using older resistive technologies (May. 31, 2012)
  When designing an SoC with a generic 32-bit MCU based on 0.18um (180 nm) processes with flash and a rich suite of analog and digital IPs, the authors found that the pre-route engines from current EDA tool vendors are tuned for smaller transistor node sizes and are not very good at the larger 180 nm geometries. Here are the steps they took to overcome such problems.
  
  
• A scalable, cost-effective phase change RAM technology (May. 22, 2012)
  We successfully developed highly scalable and cost-effective PCRAM technology based on 0.007 µm2 (4F2, 84-nm pitch) sized novel cell scheme. The chip size and density are 33.207-mm2 and 1 Gb. The device functionality and reliability were clearly demonstrated through fully integrated chip, which showed a promising feasibility for productive NVM applications.
  
  
• 3D IC 2-tier 16PE Multiprocessor with 3D NoC Architecture Based on Tezzaron Technology (May. 14, 2012)
  In this paper, we describe the design flow, architecture and implementation of our 3D multiprocessor with NoC. The design based on 16 processors communicating using a 4x2x2 mesh NoC spread on two tiers is discussed in detail and will be fabricated using Tezzaron technology with 130 nm Global Foundaries low power standard library. The purpose of this work is to accurately measure NoC performances in real 3D chip when running mobile multimedia applications to evaluate the impact of 3D architecture compared to 2D.
  
  
• How to use the CORDIC algorithm in your FPGA design (May. 14, 2012)
  Most engineers tasked with implementing a mathematical function such as sine, cosine or square root within an FPGA may initially think of doing so by means of a lookup table, possibly combined with linear interpolation or a power series if multipliers are available. However, in cases like this the CORDIC algorithm is one of the most important tools in your arsenal, albeit one that few engineers are aware of.
  
  
• Channel Core Flex: An Advanced Channeliser for Next Generation Digital Radio Receivers (May. 07, 2012)
  This paper discusses the relative merits of the various digital signal processing techniques used to channelise signals. ChannelCore Flex (CCF) exploits all of these strengths to provide a flexible channeliser architecture that is capable of supporting thousands of independently defined channels in a single FPGA. The CCF core can be tailored at build-time to support the user’s generic channel plan and required level of flexibility. The precise channel plan can then be loaded and updated at run-time. The FPGA resources required to implement CCF in a Xilinx Spartan-6 LX100 are presented for an example channel plan with 1024 channels of various bandwidths.
  
  
• Processor Optimization Pack (POP) Solutions: Enabling the Fastest Design Closure of Your ARM Cortex-A9 Processor (Apr. 30, 2012)
  This paper discusses the ARM Physical IP Processor Optimization Pack (POP) solution, the main physical IP components, the benchmarking and the techniques that can be used to drive the best possible performance while maintaining energy efficiency through leakage and dynamic power reduction. The paper will focus on key findings from ARM's POP benchmarking activity.
  
  
• Changing the paradigm for TV silicon tuners (Apr. 26, 2012)
  Although the TV market continues to mature, the underlying architectures inside the television continue to evolve to drive down prices. This article will look at key TV market trends and their effect on next-generation TV front-end solutions.
  
  
• The Challenge of the Clock Domain Crossing verification in DO-254 (Apr. 23, 2012)
  In order to meet high-performance and low-power requirements, FPGA and ASIC designs often include many separate clock domains. This practice creates Clock Domain Crossing (CDC), which occurs whenever a signal is transferred from a clock domain to another. However, these signals may cause data corruption issues, only occurring during post-layout verification, because conventional RTL verification techniques cannot detect resynchronization problems. As a consequence, critical bugs may escape the verification process and simulation does not accurately predict asynchronous silicon behavior.
  
  
• DMA IP Integration (Apr. 23, 2012)
  There are many IP’s today . These IP’s can be simple IP’s like Timer to complex IP’s like Accelerators. In Most of the cases IP’s are Integrated in standard way. There are cases where you have the option of Integrating it differently. This goes un-noticed or unable to be implemented due to time constraints. One such IP that would be discussed in this paper is DMA . This paper tries to explain idea of Integrating Direct Memory access(DMA) and Interrupt Control Unit(ICU) differently but final implementation requires some changes in IP. There is a possibility that alternate design explained below may be already implemented.
  
  
• Low power is everywhere (Apr. 19, 2012)
  Meeting power budgets for most System-on-Chip (SoC) designs today is no longer a requirement for mobile applications only. Almost every market segment today has some concern with designing in low power features—although the driving factor for why does differ among them. The primary impetus for low power design was initially driven by the mobile market due to the need for extending battery life; however, different segments do have different reasons for making power a primary design requirement.
  
  
• Enabling High Performance SoCs Through Multi-Die Re-use (Apr. 16, 2012)
  This paper gives a high-level overview of a technique for rapid design of new IC designs using multiple dice packaged in a variety of aggregations allowing for differnent performance levels and price points to be achieved. The technique relies on a new high-bandwidth low pin-count communication channel between two or more dice.
  
  
• Which USB is right for your application? (Part 3) (Apr. 09, 2012)
  In 2007, I wrote a two-part series titled “Which USB is Right for your Application” for Planet Analog (Part 1 and Part 2). Since then, several new and different “versions” of USB have been released. In this article, I discuss how they have been deployed in the market in the almost five years since.
  
  
• Encoding H.264 without External DRAM : Power and Quality Comparison (Apr. 02, 2012)
  This article compares the power consumption and quality of the generated bitstream between two Ocean Logic H.264 encoder cores : OL_H264E that uses external DRAM to store the reference frame store and OL_H264E_CFS that uses a Compressed Frame Store (CFS) technology that does not need external DRAM.
  
  
• Ensuring Successful Third Party Intellectual Property (IP) Integration (Mar. 26, 2012)
  To ensure proper IP core integration, Open-Silicon has developed a detailed and comprehensive process involving close collaboration with IP partners and the SoC design team. This article will illustrate this process by showing how Open-Silicon and Kilopass worked together on a recent project to ensure success.
  
  
• Adjusting and calibrating out offset and gain error in a precision DAC (Mar. 26, 2012)
  This application note describes the DAC errors and their sources, and then describes methods for calibrating out that error in both the analog and digital domains.
  
  
• Building a NAND flash controller with high-level synthesis (Mar. 22, 2012)
  In this article, we describe how we were able to apply a commercial HLS tool (Cadence C-to-Silicon Compiler) to a NAND flash controller with an error correction code (ECC) block. The initial ECC design was based on an ECC software program, which led to a large area due to two large arrays. We then used our domain knowledge of the ECC coding theorem to structure the code for hardware implementation.
  
  
• Integrating audio codecs in next-generation SoCs for smartphones and tablets (Mar. 21, 2012)
  This article presents the test results and discusses the business and technical challenges of integrating audio functionality into a 28-nm mobile multimedia SoC, while also offering insight on how to overcome those challenges. Some key design considerations are also explained, including scaling limitations, supply voltage requirements and system partitioning options.
  
  
• Resistive RAM for next-generation nonvolatile memory (Mar. 13, 2012)
  In this article, we review the main performance figures of hafnium-oxide (HfO2)-based RRAM cells4 from a scalability perspective, outlining their strengths as well as the main challenges ahead.
  
  
• Density Requirements at 28 nm (Mar. 12, 2012)
  In recent discussions with customers around the world, we have been hearing a surprising new message—that, at 28 nm, they have to care about density at the cell design level “like never before.” It’s surprising because density has historically been a manufacturing issue that was handled post tape-out or during chip assembly.
  
  
• Choosing the right synchronous SRAM for your application (Mar. 06, 2012)
  The choice of the right synchronous static random access memory (SRAM) is crucial for networking applications that have increased bandwidth requirements for better system performance. System designers need to be aware of the features and advantages of different synchronous SRAMs technologies to make the right memory selection for their application.
  
  
• Software generated BCH as a way to solve challenges of providing multiple configuration IP (Mar. 05, 2012)
  This article describes the idea of generating synthesizable IP core by a software tool taking an error correction algorithm of BCH (Bose-Chaudhuri-Hocquenghem) as an example. First, it gives an overview on the challenges associated with the error correction module flexibility being a trigger to study the subject. It is followed by a short introduction of NAND Flash memory and Error Correction Codes (ECC) supplemented by BCH algorithm description. In the next chapters specific implementation details are provided accompanied by highlights of configuration parameters and procedure conducted to generate selected architecture of module. Finally, the article concludes giving a very simple example how the application takes full set of parameters and translate it into the RTL source code.
  
  
• Mixed-Signal IP Design Challenges in 28 nm and Beyond (Feb. 27, 2012)
  This paper presents some key concepts necessary to design and build high-quality, mixed-signal IP in 28-nm or smaller geometries. The paper addresses specific design, layout, and verification techniques to address challenges posed in 28-nm technology nodes. Specifically, the paper focuses on three main areas where 28-nm technologies pose some unique challenges, Low-Power Design, Restricted Design Rules, and Design for Yield. Several design examples are presented, highlighting key techniques employed in the Synopsys® DesignWare® Mixed-Signal Intellectual Property portfolio.
  
  
• Clock Domain Crossing Glitch Detection Using Formal Verification (Feb. 13, 2012)
  Current System-on-a-chip (SoC) designs contain increased levels of functional and structural complexities within a single system. With the integration of multiple designs, various clock domains are introduced. In this paper, we present a solution for finding clock domain crossing glitch using a combination of formal verification and static timing analysis techniques. This paper also talks about leveraging a formal verification tool to do sequential equivalence checking between a buggy design and bug fixed design if CDC glitch is found in late design stages
  
  
• DO-254 for Dummies: IP & verification process (Jan. 23, 2012)
  Current electronic development is becoming increasingly dependent on predefined IP blocks (more than 35% of elec-tronic components currently in development use IP). It would be very surprising if the aeronautical industry (as well as other safety critical industries) could do without this key element, which is the only solution that can guarantee time to market and sustainability compatible with current requirements.
  
  
• Leverage Ethernet to improve passenger safety, comfort, and convenience (Jan. 19, 2012)
  As homes become more digitally sophisticated, consumers are developing higher expectations for connectivity and greater levels of safety and comfort in their home away from home—their vehicle. As a result, in-vehicle electronics are growing in number and complexity, keeping step with technology advancements and capitalizing on consumer expectations for a connected driving experience.
  
  
• Smart Engine for Public Key cryptography (Jan. 16, 2012)
  This white paper explains why and how the Smart Engine is ideally applied to Public Key cryptography. It provides more details about the architecture as Baco Silex has implemented it in the BA414E Public Key Crypto Engine
  
  
• AMS and High-speed Interface IP Design Enablement in GLOBALFOUNDRIES 65LPe Process Technology (Jan. 11, 2012)
  Cosmic Circuits has a strong portfolio of over 30 different Analog, mixed-signal and high-speed interface IPs in the GLOBALFOUNDRIES 65LPe technology.