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IP / SOC Products Articles

• Rethinking embedded memory (Jan. 09, 2012)
  It’s no secret that SoC architects have always wanted more on-chip memory. In fact, it’s not uncommon for SoCs to include hundreds of integrated memory cores.
  
  
• Understanding Skew in 100GBASE-R4 applications (Dec. 15, 2011)
  The 100GBASE-R4 physical layer device converts 10-lanes running 10Gbps (CAUI) to 4-lanes running 25Gbps. The conversion process is data agnostic with no provision for rate adaptation, consequently skew management is an integral part of end-to-end system performance.
  
  
• Prototyping Mesh-of-Tree NOC Based MPSOC on Mesh-of-Tree FPGA Devices (Nov. 21, 2011)
  We developed a a Network on Chip (NoC) with Mesh of Trees topology that has been proposed in literature, this particular topology is implemented into 2 different FPGA devices the Xilinx Virtex4 and the AboundLogic Raptor 750. The Raptor FPGA has a mesh of trees as routing interconnect structure, while the Virtex 4 routing is based on a Manhattan Structure. Our paper examines the potential benefits of the correspondence in topology of logical and physical interconnect. Results shows an important boost in performance level but less gain in resources usage.
  
  
• A brief primer on embedded SoC packaging options (Nov. 21, 2011)
  This article addresses the basics of packaging such as types of packages and their advantages and disadvantages, future trends, and factors to be considered while choosing a package.
  
  
• e-MMC vs. NAND with built-in ECC (Nov. 18, 2011)
  This article will explore the attributes of and differences between e-MMC and NAND with built-in ECC – as well as go into detail about the applications that are best suited for each.
  
  
• SerDes chip enables integration of multiple video streams (Nov. 18, 2011)
  This article describes a parking assistance system using four camera sensors, connected to an FPGA baseboard through the serializer/deserializer (SerDes) interface chip. Specifically, the FPD-Link product family is designed for serial interfaces of embedded displays and camera sensor systems, and also has industrial applications.
  
  
• Building a high-performance camera for wood inspection (Nov. 09, 2011)
  This high-performance wood-inspection system is based on a VITA1300 image sensor and an XEM5010 FPGA integration module
  
  
• Stellamar's all-digital, fully-synthesizable, analog-to-digital converters for Microsemi FPGAs (Nov. 09, 2011)
  This all-digital ADC requires no analog block design; only a few passive components are necessary
  
  
• Design and Implementation of an OCP-IP Compliant 64-Node Butterfly Network on Chip on Multi-FPGA (Nov. 07, 2011)
  In this paper, we report the design and multi- FPGA chip implementation of a 64-node butterfly network based on MPSOC. Our Network is placed and routed automatically on the 4 FPGA included in Eve Zebu-UF4 platform.
  
  
• Overcoming 40G/100G SerDes design and implementation challenges (Nov. 02, 2011)
  Increasingly higher-bandwidth requirements continue to drive development and demand for 40G and 100G systems. To implement these link speeds, SerDes devices must meet tighter performance specifications, with extremely high speeds running at extremely low bit-error-rates (BER).
  
  
• Distributed Video Coding: Adaptive Video Splitter (Oct. 31, 2011)
  In this paper, an adaptive video splitter (AVS) design and implementation details, which can also improve RD performance with significantly higher motion video sequences, are presented. This paper is backed up with experience of developing entire DVC codec C model, which is presented in authors other submitted paper.
  
  
• Simple ways to manage different clock frequencies of audio codecs (Oct. 26, 2011)
  Audio processing is essential to many consumer electronic applications such as mobile phones, MP3 players and a host of other products. While size and power consumption are often critical SoC design requirements, the market demands high-quality high fidelity (Hi-Fi) audio capabilities.
  
  
• The basics of low power programming on the Cortex-M0 (Oct. 26, 2011)
  The ARM Cortex-M0 processor has been designed to provide low-power advantages over other processors. In this article I will discuss how some of these features can be used to advantage in programming for this architecture.
  
  
• Big.LITTLE processing with ARM Cortex-A15 & Cortex-A7 (Oct. 25, 2011)
  This white paper presents the rationale and design behind the first big.LITTLE system from ARM based on the high-performance Cortex-A15 processor, the energy efficient Cortex-A7 processor, the coherent CCI-400 interconnect and supporting IP.
  
  
• Implementing high Speed USB functionality with FPGA- and ASIC-based designs (Oct. 19, 2011)
  A wide range of FPGA-based applications exist that can benefit greatly from the addition of a high speed USB interface…
  
  
• Argument for anti-fuse non-volatile memory in 28nm high-K metal gate (Oct. 17, 2011)
  One function that continues to be challenging for on-chip integration is non-volatile memory (NVM) despite its many advantages. At smaller process geometries, especially 28nm HKMG, the challenges to integrating NVM such as flash, pseudo flash, and e-fuse are effectively addressed with an anti-fuse solution.
  
  
• Multi-FPGA NOC Based 64-Core MPSOC: A Hierarchical and Modular Design Methodology (Oct. 10, 2011)
  With the increasing need for real time complex applications, number of processors in the same MPSOC design is becoming a critical parameter to evaluate its performance.
  
  
• Designing a high-definition FPGA-based graphics controller (Oct. 06, 2011)
  Recently, one of our clients came to us looking for a solution to display graphics on LCD monitors. We were informed that any data was to be is generated by a separate device and fed to the graphics controller using an external microcontroller.
  
  
• Debunking the myth of the $100M ASIC (Oct. 04, 2011)
  A false belief that leading-edge chips cost up to $100 million to develop has severely decimated levels of venture capital investment in semiconductors, diminishing innovation in our industry and our economy. The fact is, engineers can create a profitable chip company with less than $2 million of total investment. I know because we have done it.
  
  
• SerDes in High-Reliability, Long Reach Systems (Sep. 19, 2011)
  The paper explores the challenges facing designers implementing systems that are compliant to 10GBASE-KR and CEI11-LR standards. These systems can be 40-50” with multiple connectors and it is desirable to have bit-error-rates (BER) of 10-15 to 10-18 for high-reliability applications, going beyond the specification for these real-world channels.
  
  
• FPGA-based Ethernet switches for real-time applications (Sep. 08, 2011)
  Lattice Semiconductor and Flexibilis have released a Gigabit Ethernet Switch IP core that is scalable, non-blocking, and extensible.
  
  
• USB3.0 application building using low performance 8-bit microcontroller (Sep. 06, 2011)
  This article presents the aspects of building USB3.0 application using low performance 8-bit microcontroller taking an 8051 derivative as an example. First it gives a technical overview of the USB technology and its performance. In the next chapters the example architectures are discusses followed by target applications based on them.
  
  
• Many-Core: Finding the Best Multi-Processing Tile (Aug. 30, 2011)
  A project to create an optimal many-core IP tile tackles the need for massive emulation capability.
  
  
• Hot Chips: the puzzle of many cores (Aug. 25, 2011)
  Papers at Hot Chips 2011 suggest that emphasis is shifting from multicore to manycore.
  
  
• Ultra Low Jitter Wide Band LC PLL (Aug. 22, 2011)
  The accelerating need for ever higher data rates and serial I/O density sets demanding performance requirements for current and next generation SerDes transceivers. The PLL is the key to determining high speed link capabilities, since high quality clocks are required to meet bit error rate (BER) specifications of 10-12 to 10-15. An ultra-low jitter wideband LC PLL has been developed to meet the exacting requirements of today's systems.
  
  
• Distributed Video Coding (DVC): Challenges in Implementation and Practical Usage (Aug. 15, 2011)
  Distributed Video Coding (DVC) is a new coding paradigm for video compression. This paper highlights gaps and challenges in implementation of DVC and its practical usage.
  
  
• SOCs: IP is the new abstraction (Aug. 11, 2011)
  Reusable IP, not system-level language, has become the new level of abstraction.
  
  
• The Importance of True Randomness in Cryptography (Aug. 08, 2011)
  Creating Random Numbers is hard. Especially if all you have available to do it, is digital hardware and deterministic software. Where is the randomness in that? Both are designed to behave predictably, each time, every time. Therefore, hardware and software designers, trying to find unpredictability, have to look outside of their normal operating environment to find it.
  
  
• Interconnect Solutions for 40G/100G Systems (Aug. 01, 2011)
  One of the key challenges with supporting 40G/100G links is that the SerDes must not only support emerging standards such as XLAUI (40G Ethernet) and CAUI (100G Ethernet) but must continue to support current and legacy interfaces such as 1Gbps Ethernet (SGMII) and 10Gbps Ethernet (XAUI). Multi-protocol support is essential to managing the transition to higher data rates while still supporting legacy standards.
  
  
• Design guidelines for embedded real time face detection application (Aug. 01, 2011)
  Much like the human visual system, embedded computer vision systems perform the same visual functions of analyzing and extracting information from video in a wide variety of products.