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IP / SOC Products Articles

• SPVR: An IP core for Real-Time Speaker Verification (Jul. 18, 2011)
  This paper aims at presenting an IP core whose purpose is to perform real-time speaker verification. The IP core can be used as part of a system to check if the speaker is really the one (he or she) who claims to be.
  
  
• ARM Mali-T604 tips mobile graphics, computing, and IP trends (Jul. 07, 2011)
  The ARM Mali graphics core is a departure from years of evolution in the rendering hardware, but points to the future of IP.
  
  
• Application Driven Network on Chip Architecture Exploration & Refinement for a Complex SoC (Jun. 20, 2011)
  This article presents an overview of the design process of an interconnection network, using the technology proposed by Arteris.
  
  
• Moore's Law, the bifurcation of the semiconductor industry and 3-D integration (Jun. 17, 2011)
  With all the gloom and doom facing the semiconductor industry and especially with the "end of Moore's Law" coming up soon as many experts predict, let's look at several facts relating to the unbelievable ride the industry has had for the last 40 years
  
  
• Basics of SoC I/O design: Part 1 - The building blocks (Jun. 16, 2011)
  Integration of analog with digital and increase in on chip features in mixed-signal controllers demand more complex I/O structures as well, but are often the most neglected features of a chip. This two part article will provide the basics for allowing developers to optimize their performance and functionality. Part 1: The I/O building blocks.
  
  
• Basics of SoC I/O design: Part 2 - Hot swap & other implementation issues (Jun. 16, 2011)
  Having dealt in Part 1 with some of the basics of SoC I/O pin assignment, in this second part we will deal with a variety of implementation issues, including hot swap, interrupts, pin assignments and Interfacing with the devices being operated at voltage other than SoC’s core voltage
  
  
• Understanding SD, SDIO and MMC Interface (Jun. 13, 2011)
  This white paper presents very important information for managers, engineers, and system architects who want to broaden his/her knowledge of interfacing with removable data storage devices. There are many different aspects of SD and MMC interfacees and this white paper organize them into a very easy to understand format.
  
  
• Silicon Qualified SuperViC: the only way to safe SoC integration (Jun. 13, 2011)
  System integrators often encounter problems on application boards too late in the design cycle, when bringing together Virtual Components (ViCs of silicon IPs) into a system. Some ViC performances may be degraded at higher levels (SoC and PCB), and thus the final system does not perform as well as expected. In other words, assembling high-performance ViCs together does not guarantee high-performance SoCs or systems when fundamental integration aspects are not addressed or key issues are violated during the integration process.
  
  
• A Case for Custom Power Management ASIC (Jun. 06, 2011)
  As more functionality has been added to the devices, the power requirements have increased. As the power requirement grows, the capacity of the battery has to be increased, increasing the space occupied and its weight. This makes the battery one of the bulkiest component in the handhelds.
  
  
• The Sony PlayStation 3 hack deciphered: what consumer-electronics designers can learn from the failure to protect a billion-dollar product ecosystem (Jun. 06, 2011)
  What threats are designers of consumer-electronic products up against when trying to secure their platforms against attacks? A robust platform security system that begins with a clear set of security objectives is key to meeting the attacker challenge and surviving and recovering from similar onslaughts.
  
  
• Improving today's multimedia products with 3rd-party audio IP solutions (Jun. 06, 2011)
  In the multimedia market, there is insatiable consumer demand to create, transmit and share digital audio and video content. This demand is driving explosive growth in consumer electronic devices requiring audio post-processing software IP to play digital content without comprising audio fidelity or the consumer listening experience.
  
  
• Two methodologies for ASIC conversion (Jun. 02, 2011)
  ASIC vendor eASIC's announcement of a conversion path from their Nextreme structured devices to a fully cell-based ASIC offers an interesting opportunity to reflect on conversion methodologies. Comparing it to a recent discussion of the KaiSemi conversion flow, which takes a design from an FPGA to a cell-based ASIC, further illuminates some of the important choices that come up in reworking an existing design. The two approaches are conceptually similar, but practically quite different.
  
  
• Advanced Power Management in Embedded Memory Subsystems (May. 16, 2011)
  This paper addresses minimizing low-power design complexity with power, performance and density optimized IP. It covers the power problem, and the complexity of designing with multiple power domains in SoC designs that contain embedded memory. The paper includes the trade-offs and benefits of various power management features as well as the implementation of the design for superior testability by providing optimal test resource partitioning.
  
  
• STAC: Advanced inter-die communication Technology (May. 16, 2011)
  This paper outlines recent a new architecture for implementing a communication channel between two highly-integrated dice. It shows how the on-chip interconnect can be extended to bridge between chips while retaining high bandwidth and low latency. In addition, the technique allows other signals to be integrated into this communication channel without side band signals in a low pin-count and low power architecture. This arrangement provides a universal link which allows the cooperation of multiple chips within a package which may have been designed independently.
  
  
• NoC Interconnect Improves SoC Economics (May. 09, 2011)
  The concise research paper, "NoC Interconnect Improves SoC Economics: Initial Investment is Low Compared to SoC Performance and Cost Benefits," by Objective Analysis Semiconductor Market Research, provides quantitative data from user experiences comparing the costs and benefits of implementing network on chip SoC interconnects versus traditional bus and crossbar interconnects.
  
  
• Embedded antifuse NVM: A mission critical IP for display driver ICs (May. 02, 2011)
  This Product How-To article discusses use of antifuse nonvolatile memory in display driver ICs (DDI) and touch sensor controllers and how proprietary technology from Kilopass can be used to make NVM an integral part of a system-on-chip design.
  
  
• Systematic approach to verification of a mixed signal IP - HSIC PHY case study (Apr. 21, 2011)
  This paper discusses verification process of a mixed signal core of an HSIC PHY. After explaining the specific topic related with HSIC comparison to USB, the verification strategy is shown. The strategy is explained from the top level point of view, and detailed description is covered in subsequent sections. In following sections the system level testbench and interoperability testbenches are explained parallel to local testbenches for analog block characterization.
  
  
• Cache Evaluation Software: A Dynamically Configurable Cache Simulator (Apr. 18, 2011)
  The memory hierarchy (including caches and main memory) can consume as much as 50% of an embedded system power. This power is very application dependent, and tuning caches for a given application is a good way to reduce power consumption. However application programs are complex and include many subroutines, each of them having their own optimal cache configuration. We developed a low power dynamically reconfigurable cache controller and its simulator called Cache Evaluation Software.
  
  
• M-PHY benefits and challenges (Apr. 13, 2011)
  The M-PHY supports plesiochronous as well as mesochronous operations, speeds from 10Kbps up to data rates of 6Gbps while maintaining low power operation, achieving low electro-magnetic-interference (EMI), supporting a variable number of links, sub-links, and data lanes, multiple media options, and a growing number of use-case in traditional and non-traditional mobile applications.
  
  
• Minimal Effort Chip Design Using IP (Apr. 11, 2011)
  In order to speed up design cycles and to reduce development costs, use of external IP is increasingly becoming more popular. However, this IP based design is not free of considerable effort and saves only about half of the effort required to develop the IP internally. The concept of Intelligent Design Automation (IDA) is presented here which uses intelligent algorithms such as matchmaking algorithm, rating systems, fuzzy logic, and multi-criteria optimization. This paper also presents the idea of IP Integration Automation,or I2A, tools.
  
  
• The Power and Bandwidth Advantage of an H.264 IP Core with 8-16:1 Compressed Reference Frame Store (Apr. 04, 2011)
  Power is an increasingly important consideration for the majority of system designers. This is particularly true in the case of small handheld consumer devices such as cameras, camcorders and mobile phones. In such devices, video compression technology is used that relies on power hungry DRAMs to store the reference frames during the encoding and decoding process.
  
  
• Complete NAND Flash Solution: Logic, PHY and File System Software (Mar. 28, 2011)
  NAND FLASH memories are non-volatile, inexpensive and of high capacity. These characteristics make these devices ideal for fulfilling the storage requirements in the exploding mobile device market.
  
  
• Analog IP for multimedia SoCs: an eye on a world of essential analog features (Mar. 23, 2011)
  This article unveils how the analog functions that are built into an analog IP multimedia subsystem should be carefully selected to address the particular application requirements while guaranteeing the smallest silicon area and the lowest power consumption, a two-fold challenge that is commonly faced today by both system-on-chip (SoC) integrators and IP providers.
  
  
• Analog switches in D-PHY MIPI dual camera/dual display applications (Part 2 of 2) (Mar. 17, 2011)
  When inserting an analog switch, the key influencing factor is still the incident wave response, as the switch can be seen as a discontinuity. The switch RC characteristics have to be optimized to facilitate good “eye” performance by minimizing reflections and edge rate degradation.
  
  
• A 55-nm Ultra Low Leakage SRAM Compiler with Optimized Power Gating Design (Mar. 14, 2011)
  In this paper an optimized power gating design on a 55-nm Static Random Access Memory (SRAM) compiler is presented. Two low leakage modes: retention and sleep mode are discussed. The arrangement of power gating (P.G.) MOS is especially considered for the compiler design. The proposed method achieves an obvious advantage in leakage control of low leakage mode for memory compiler. Simulation data shows a 4× leakage reduction for retention mode, and a 50× leakage reduction for sleep mode for a 512k density instance compared to original design.
  
  
• Analog switches in D-PHY MIPI dual camera/dual display applications (Part 1 of 2) (Mar. 14, 2011)
  This article describes how, with the use of analog switches, the legacy processors can easily interface with dual cameras or dual displays without impacting the current system architecture and can, in actuality, enhance system performance by isolating the transmission line effects of the second camera (or display) loading the MIPI bus.
  
  
• Using PCI Express as a fabric for interconnect clustering (Mar. 08, 2011)
  A number of interconnect technologies are vying to replace GbE, with the top contenders being 10 Gigabit Ethernet (10GbE), InfiniBand (IB) and PCI Express (PCIe). The latter, with its advanced capabilities, makes a strong case for becoming the ideal backplane interconnect solution.
  
  
• CPUs in FPGAs: many faces to a trend (Mar. 07, 2011)
  Whether as synthesizable soft cores or hard cores on the die, CPUs are showing up in more FPGA designs, bringing with them important challenges for designers.
  
  
• Adding encryption to disk drives is made easy using an IP core (Mar. 03, 2011)
  The availability of low-cost IP cores that implement AES-128 or AES-256 opens up the possibility that all drives can have high-grade encryption as standard.
  
  
• MIPI™ MPHY - An introduction (Feb. 28, 2011)
  Recognizing the need for high bandwidth pipes, the MIPI alliance has been defining standards for these serial interfaces. D-PHY, which was ratified 1.5 years ago but with a near final version for 3 years, supports 1Gbps per lane. The M-PHY specification, whose 1.0 version is about to be ratified, supports about 1.25Gbps/1.5Gbps and has options to support 2.5Gbps/3Gbps and 5Gbps/6Gbps per lane.