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IP / SOC Products Articles

• Advancing Network Packet Management for Converged NIC (Feb. 09, 2012)
  In a Data center, with the advent of Virtualization and Virtual Ethernet Bridging, the server to network edge is becoming an increasingly important area of the infrastructure. The most common types of networks used in enterprise Data Centers are Ethernet for LAN and FC for SAN and are converging. Fiber Channel (FC) is a lightweight, high performance protocol usually with in a SAN (limited area), where as iSCSI running over traditional TCP/IP protocols (routable) and existing Ethernet Infrastructure. These have different topologies, administrators, security, and performance requirements.
  
  
• Optimizing System Management in the Platform SoC Era (Jan. 26, 2012)
  Consumer focused SoCs have evolved into platform architectures that are now being driven by requirements from operating systems such as Android, iPhone. Linux, and Windows and the thousands of applications they support. Overtime more of the system is moving into silicon . As a result, system management functions have moved into the SoC. Traditional feature based regression testing at the silicon level must now be increasingly complimented with complex system level testing in order to maintain a high level of system coverage across SoC road maps.
  
  
• icyflex: an ultra-low power DSP core for portable applications (Nov. 14, 2011)
  The icyflex family of ultra low power 16/32-bit RISC processor cores developed by CSEM offers a flexible architecture that allows for different com-binations of control and DSP functionality. These processors target applications requiring long battery life at the same time as on-chip processing power. Three silicon-proven icyflex cores are available, consuming as little as 6 μW/MHz.
  
  
• Performance Measurements of Synchronization Mechanisms on 16PE NOC Based Multi-Core with Dedicated Synchronization and Data NOC (Sep. 08, 2011)
  Multi-core are emerging as solutions for high performance embedded systems. Although important work have been achieved in the design and implementation of such systems the issue of synchronization mechanisms have not yet been properly evaluated for these targets. We present in this work synchronization performance evaluation results on a 16PE NOC based multi-core which we designed and implemented on a single FPGA chip. All reported results come from actual execution and show hybrid synchronization mechanisms best fit the multi-core configurations.
  
  
• Performance Evaluation of Inter-Processor Communication Mechanisms on the Multi-Core Processors using a Reconfigurable Device (Aug. 04, 2011)
  . In this paper, we propose several inter-processor communication mechanisms for two multi-core processors on an FPGA as the primitive operations for the system tasks and evaluate them. We adopted NIOS II processor as the embedded processors and the TOPPERS/ FMP kernel as the operating system for multi-core processor.
  
  
• Virtual Channels Hardware Support in Switches in Relation to NoC Costs, Functions and Features (Feb. 21, 2011)
  In this article we consider dependencies between virtual channels hardware implementation features and packet transmission timing parameters in a network-on-chip, as well as possibilities for different classes of services support.
  
  
• Routing Congestion: The Growing Cost of Wires in Systems-on-Chip (Feb. 21, 2011)
  This paper presents trends in technology, introduces packet based network-on-chip as a means of enabling configuration link widths, shows experimental results, and describes other benefits of packet-based interconnect networks.
  
  
• Integration Optimized SuperSpeed USB3.0 IP from Cadence - Delivering Superior Value to the SOC Designer (Feb. 14, 2011)
  Designs are moving towards a hierarchical structure, collection of individual subsystems each with a local interconnect CPU, DSP, and memory, and a global interconnect tying all these subsystems together, along with intelligent Interface IP, and multichannel memory. The pain points faced by the customer in today's world, is in obtaining and integrating enormous amount of IP, having to verify a system that comprise of SOC hardware and software, creation and validation of software, and not to mention the least, hitting schedule and budget.
  
  
• Importance of Dynamic Programming for Achieving Hard Breakdown in Anti-Fuse Technology (Jan. 31, 2011)
  As System-on-chip (SOC) developers continue to look for ways to reduce cost and time to market, it is important to consider the different non-volatile memory (NVM) options that add flexibility to their products. Over the last few years, the NVM market has been flooded with new solutions. Now, having customers weigh the benefits of reliability, options, and costs during project development is even more critical. With antifuse vendors targeting a wider range of functionality and products, noting the reliability concerns of reaching hard breakdown (HBD) compared to soft breakdown (SBD) is vital.
  
  
• 7 myths of analog and mixed-signal ASIC design (Jan. 28, 2011)
  Application specific integrated circuits (ASICs) typically conjure up the notion of massively complex logic chips containing tens or hundreds of thousands (even millions) of transistors configured to solve a customer’s unique set of problems.
  
  
• Multiband architecture for high-speed SerDes (Jan. 20, 2011)
  The authors explore a multiband architecture for a 25 Gbps SerDes, where the channel in each sub-band is approximately frequency flat, eliminating need of an equalizer in the receiver.
  
  
• How to implement *All-Digital* analog-to-digital converters in FPGAs and ASICs (Jan. 19, 2011)
  All-Digital Digital-to-Analog Converters (DACs) offer 50% lower power, 68% smaller area, process technology independence, reduced risk and cycle time, digital integration and synthesis, and easier radiation-hardened design.
  
  
• Designing an FPGA-based graphics controller (Jan. 17, 2011)
  This FPGA-based control module involves an integration of three controllers (SVGA, SDRAM, and FLASH), thereby providing additional functionality to any embedded system.
  
  
• Mixed-Signal Designs: The benefits of digital control of analog signal chains (Jan. 17, 2011)
  Mixed-signal designs combine the most powerful features and advantages of both analog and digital circuitry. One common mixed-signal architecture is a chain of analog signal blocks, each controlled by digital logic. These designs take advantage of the stability and algorithmic capabilities of digital logic to control traditional analog circuitry.
  
  
• Is there a "one-size fits all" SOC PLL? (Jan. 10, 2011)
  Like most types of circuits, there is no such thing as a "one size fits all" PLL. This article will explore the trade-offs in PLL performance and design and look for a solution to most SOC PLL needs.
  
  
• Configurable VESA - VGA and DVI Test Pattern Generator (Jan. 03, 2011)
  This paper is presented with the Video Graphics Array (VGA) and Digital Visual Interface - Digital (DVI-D) test pattern generator solution with display monitor timing specification as per the Video Electronics Standards Association (VESA) to address the VGA and DVI-D video processors RTL verification and chip validation requirements.
  
  
• Understanding the basics of PLL frequency synthesis (Dec. 27, 2010)
  Configuring a phase locked loop (PLL) for a given frequency synthesis application can simultaneously be both a quick-and easy-process as well as a time-consuming, tedious, and iterative process. This dual nature in PLL system design arises from the number of loop parameters that need to be appropriately dialed in for a given application.
  
  
• Understanding and selecting higher performance NAND architectures (Dec. 10, 2010)
  This article is intended to help system and memory subsystem designers understand the differences and benefits of some of the newer NAND architectures.
  
  
• Hyper pipelining of multicores and SoC interconnects (Nov. 04, 2010)
  In this paper, a method is discussed: How the functionality of a core can be multiplied by just adding registers to the core. Not only does this result in less area usage compared to its individual instantiations, but it can also have a substantial beneficial impact on the system performance as a whole. This method is called “hyper pipelining”.
  
  
• SATA Connectivity solutions for Xilinx FPGAs (Oct. 18, 2010)
  This Whitepaper gives an overview over the Serial ATA (SATA) protocol and the implications when integrating SATA into an FPGA-based programmable system. Besides details of the different protocol layers, we will discuss the hardware and software components for building a complete, reliable, high-performance SATA solution by utilizing a design platform from Missing Link Electronics (MLE).
  
  
• How to Choose Great IP (Oct. 04, 2010)
  Many chip designers use IP to improve their productivity, but unfortunately not all IP is created equal. Ed Bard, senior director of marketing, IP, and Ralph Morgan, vice president of engineering, IP, both of Synopsys, suggest that to separate the good from the bad, design teams must exercise proper due diligence when selecting IP.
  
  
• Avoiding design errors in 1394-based external storage systems (Sep. 28, 2010)
  While IEEE 1394/Firewire is a popular and proven standard familiar to many system designers, there is still the potential to make design errors that can compromise performance. Here are some tips for avoiding such problems
  
  
• The basics of SerDes (serializers/deserializers) for interfacing (Sep. 17, 2010)
  SerDes (serializers/deserializers) are devices that can take wide bit-width, single-ended signal buses and compress them to a few, typically one, differential signal that switches at a much higher frequency rate than the wide single-ended data bus.
  
  
• Conquering the memory bottleneck (Sep. 14, 2010)
  The evolution of high-bandwidth, consumer system on chip (SoC) devices is driving new design requirements as developers look for innovative ways to conquer bandwidth and efficiency issues on-chip. Today’s most popular home entertainment and mobile devices, such as smart phones, pad computers, high-definition TVs and personal media players, require an ever increasing number of processors that are dependent on sharing the same DRAM pipe. This has generated a substantial efficiency bottleneck for SoC designers and system architects.
  
  
• Extreme Design: Realizing a single-chip CMOS 56 Gs/s ADC for 100 Gbps Ethernet (Aug. 26, 2010)
  A 100-Gbps coherent receiver needs four 56-Gs/s analog/digital converters (ADCs) and a tera-OPS DSP which dissipate only tens of watts. This paper discusses the forces pushing towards a single-chip CMOS solution, and the challenges in realizing this.
  
  
• Harness speed, performance, signal integrity, and low current advantages of 65nm QDR family SRAMs (Aug. 24, 2010)
  This article describes in detail the advantages of the 65nm technology QDR family devices over their 90nm technology equivalent and provides guidelines for simplifying the migration from 90nm to 65nm technology.
  
  
• Dual core architectures in automotive SoCs (Aug. 24, 2010)
  Automotive SoCs have traditionally been single core, since not much computational work or high end applications were targeted on them. Automotives were simpler, so were the applications and so were the SoCs. As more and more electronics made room in the automotives, the complexity of the SoCs kept on increasing. Now the focus is to have most of the automotive under electronic control.
  
  
• MIPI M-PHY takes center stage (Jul. 12, 2010)
  The curtain is up and the M-PHY specification is taking center stage, positioned to handle the many different roles required for a faster, more reliable, physical interface layer (PHY Layer) on mobile devices.
  
  
• SuperSpeed USB (USB 3.0): More than just a speed increase (Jul. 05, 2010)
  SuperSpeed USB (USB 3.0) has been getting a lot of attention now as products become available in the market. The most obvious benefit is the more than 10 times increase in speed over USB 2.0 high-speed; 480 Mbps to 5 Gbps – but there are several others. This article looks at what is new and better with SuperSpeed USB protocols and power management versus USB 2.0.
  
  
• Multiplexed Energy Metering AFEs Ease ASIC Integration and Provide Significant Cost Reduction (Jun. 21, 2010)
  Today’s energy metering standards demand higher accuracy and lower power consumption which, in turn, challenges system designers to deliver more competitive AFEs. This article reviews those challenges and presents a solution based on a multiplexed channel architecture that delivers ultra-high resolution, along with very low-power consumption and silicon area.