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IP / SOC Products Articles

• Power Optimization in Image Superscalar IP (May. 23, 2011)
  In this paper we have present an optimize power aware architecture named as “Cluster Memory Architecture”. This Architecture is implemented in Design and Development of 60 fps Super Scalar IP which can convert 60 VGA Frame to Full HD Frame per second. This architecture ensures similar or reduction of power consumed for same size Single Port SRAM Memory and similar performance as Dual Port RAM. This architecture also facilitates for Switching Off the un-used segment of the memory
  
  
• COMSIS 802.11n: an IP to Reuse - a flexible platform for Design (May. 09, 2011)
  In this paper, we present 802.11n Comsis IP and the Comsis WiFi evaluation board. First, we summarize 802.11n recommendation features explaining why the MIMO technology performs so well.
  
  
• Implementing Different Power Features in an IP (Apr. 04, 2011)
  One of the challenges for present SoC designers is to ensure that their SoCs consume least power. Since almost all SoCs use a set of IPs, it’s important for the IP providers to give different power reduction options in their IPs, enabling the SoC designers to design a power optimized chip. This paper primarily focuses towards IP design and verification engineers and lists some useful power reduction features that can be implemented in an IP.
  
  
• Verification of USB 3.0 Device IP Core in Multi-Layer SystemC Verification Environment (Mar. 17, 2011)
  The paper describes the methodology used for functional verification of the USB 3.0 device controller core. The core model has been developed at two different levels of abstraction: RTL model for synthesis and SystemC TLM model for high speed simulation, early software development and early test-bench creation.
  
  
• Hardware Solutions to the Challenges of Multimedia IP Functional Verification (Feb. 14, 2011)
  This paper discusses the functional verification of IP cores and problems which arise during their implemenation in today’s advanced applications. First, the usual approach to functional verification is presented together with its common difficulties. The next part features an example of hardware verification environment which was used for verification of the Evatronix JPEG 2000 encoder multimedia IP core in order to illustrate this paper’s thesis. After a short description of the JPEG 2000 image compression algorithm, the structure of the environment is presented. Then the manner of test cases preparation is described as well as criteria used to determine whether a particular test is passed or failed. Finally, numerical results of hardware verification experiment are presented with some comments which conclude the paper.
  
  
• Advancing Network Packet Management and Security Using Silicon Based Subsystem IP Solutions (Jun. 17, 2010)
  The growth of the Internet continues to drive the need for faster network packet management and improved network security. One way to improve both performance and security effectiveness is to reduce the physical number of hardware and software components that make up OSI Layer 2-4 solutions in the network using an integrated silicon based “subsystem” approach.
  
  
• Low Power Verification of Connectivity IP cores - a USB HS-OTG Case Study (Jun. 14, 2010)
  This paper focuses on the verification challenges and the methodology used to verify a low power design that embeds a combination of techniques to save power.
  
  
• Building Cost Effective and Robust SoC-based Network Appliances (Jun. 01, 2010)
  Krishnan Venkataraman is VP of Engineering at MosChip Semiconductor Technology Ltd.
  
  
• Breaking the 2 Giga Access Barrier: Overcoming Limited I/O Pin Counts (May. 31, 2010)
  Cisco’s Visual Networking Index forecasts that the Internet growth will quadruple by 2013. Projected Internet traffic will approach 1 Zettabyte (1 trillion Gigabytes) per year. To support this amazing trend, the next generations of networking equipment must offer new levels of packet forwarding rates and bandwidth density. This in turn will necessitate new generations of packet processors and the memory subsystems to support these increased demands. MoSys is stepping up to this challenge by introducing a new class of device to accelerate access to packet forwarding information, statistics calculations and packet storage.
  
  
• Selecting the right Nonvolatile Memory IP: Applications and Alternatives (May. 25, 2010)
  With the myriad NVM technologies available, the challenge for system engineers is to do a thorough and critical assessment of the real needs their designs and second, to to understand the benefits and trade-offs for each.
  
  
• The 'off-the-shelf' IPs for today's SoCs (May. 24, 2010)
  Today SoC designs are highly complex with many functionalities. Do these functionalities need to be developed entirely in-house? Rather not! Here is some advice on when you should choose third party IP vendor instead of developing standard component in-house.
  
  
• A Novel Mesh Architecture for On-Chip Networks (May. 06, 2010)
  2D Mesh is a very popular topology in Network on Chip due to its facilitated implementation, simplicity of the XY routing strategy and the network scalability. On the other hand, 2D Mesh has some disadvantages such as long network diameter as well as energy inefficiency because of the extra hops. Due to this, in this work, we propose a novel NoC topology called Diametrical 2D Mesh and related shortest path routing algorithm called Extended XY.
  
  
• Integrating analog video interface IP into SoCs delivers superb image quality (Part II) (May. 03, 2010)
  This two-part series discusses the implementation of analog video interfaces that can be embedded into complex SoCs. Part two provides a detailed review of the analog video interface receiver, which is based on a video analog front-end. Key characteristics are covered, highlighting the special features embedded into the IP that allow it to recreate a high-quality image on the destination side.
  
  
• Choosing the best Standard Cell Library without falling into the traps of traditional benchmarking methods (Apr. 26, 2010)
  Assessing the comparative performances of several Standard Cell Libraries in a reliable way is a tricky project as it deals with statistical issues. The objective of this paper is dual. The first objective is to demonstrate that the « cell-by-cell » approach to compare libraries is inconsistent with actual performances results obtained after P&R of libraries on a logic circuit. The second objective is to present benchmarks and methods to compare efficiently and reliably different libraries with different architectures (e.g. CCSL versus RCSL).
  
  
• Maximizing the value of your IP (Apr. 23, 2010)
  There is no doubt that leveraging IP for reuse is here to stay. The economic and time-to-market advantages are too enormous to forego. However, there are serious challenges to overcome given the high cost of verification and the risk of collateral design damage consequential to RTL modification.
  
  
• Developing a test plan to make your design HDMI 1.4 compliant (Apr. 15, 2010)
  How to use the Agilent E4887A TMDS signal generator to test the quality of HDMI system cables and connectors, and other components for compatibility with Version 1.4 of the spec.
  
  
• PP: An Application-Specific Processor for Manycore Architectures (Apr. 12, 2010)
  The Protocol Processor (PP) is an application-specific processor employed in several products at Lantiq. In this paper we discuss the limitations of simple application-specific processors within manycore architectures and we report on our work on the PP to eliminate or mitigate these limitations.
  
  
• Integrating analog video interface IP into SoCs delivers superb image quality (Part I) (Apr. 07, 2010)
  This two-part series discusses implementation of analog video interfaces that can be embedded into complex SoCs. Part one focuses on the transmitter part of the analog video interface, which is essentially a digital-to-analog converter with video performance, and discusses the characteristics of the source and of the transmission medium.
  
  
• DDR3 memory interface controller IP speeds data processing applications (Apr. 06, 2010)
  In order to fully capitalize on the benefits of DDR3 memories, it is important to have an efficient and easy to use DDR3 memory interface controller. A video processing application provides a good example of the key requirements of a DDR3 memory system and the features needed from a DDR3 Interface in similar stream-oriented data processing systems.
  
  
• Design of an image-processing device for cost-sensitive, high-volume applications using a novel dynamically reconfigurable technology (Apr. 05, 2010)
  Many devices could benefit from programmability, but high-volume, cost-sensitive applications often force device manufacturers to use hard-wired RTL design techniques for reasons of end device cost. This results in the need for multiple silicon implementations to support different device variants, and means that device manufacturers are slow to respond to changing market requirements owing to the time taken to redesign, verify, manufacture and test a new device variant. Though programmability is highly desirable, the complete flexibility of function provided by a CPU or DSP-based solution is rarely necessary. This paper illustrates a design approach that uses a novel dynamically reconfigurable logic (DRL) technology to produce a device that is just reconfigurable enough to meet the flexibility requirements of the manufacturer whilst not imposing a significant size or power overhead compared to traditional RTL-based design techniques.
  
  
• A Flexible, Field-programmable ROM Replacement (Mar. 15, 2010)
  For large amounts of on-chip code and data, mask read-only memory (ROM) provides an inexpensive and easily programmed storage mechanism. However, the inability to configure ROM after wafer processing means that information stored in the ROM cannot be changed in the field. Antifuse one-time programmable (OTP) provides a flexible, field-programmable alternative to ROM. An antifuse-based bit cell uses controlled, irreversible thin (gate) oxide breakdown to program a bit.
  
  
• Initial Investigations into UML Based Architectural Reference Patterns for Set-Top Boxes (Mar. 08, 2010)
  This paper analyses a leading-edge Set-top Box (STB) design for architecture reference patterns. Specifically, the following contributions are made: (i) identifying and documenting (in UML) STB architectural reference patterns, and (ii) providing empirical (quantitative) analysis of pattern use.
  
  
• Selecting an embedded MCU: How to avoid evaluation trap? (Mar. 08, 2010)
  The main goal of this article is to focus on the difficulties encountered by SoC integrators when selecting an embedded microcontroller (MCU). Indeed, the selection is based on MCU performances, but the comparison can be difficult and compromised when considering all the parameters influencing these performances.
  
  
• Embedded Symmetric MultiProcessing system on a SoC with 1.6GHz PowerPC IP in 45nm (Mar. 01, 2010)
  Because the dimensions of lithography are now closer to the fundamental physical limits, scaling is more and more difficult and thus multi-core processor solutions are just starting to be more popular in the embedded area. This paper describes in details the features that allow SoCs to be built with up to eight 1.6 GHz PowerPC CPU cores in an embedded system supporting Symmetric Multiprocessing (SMP) architecture. The balancing between CPU execution speed, memory bandwidth and latency, and coherency overhead has been the objective of the design of the PLB6 and the L2 Cache IP's, to reduce as much as possible the drop-off in performance-per-core inherent in an SMP approach.
  
  
• Evolving to a Total IP Solutions to Accelerate SoC Design (Mar. 01, 2010)
  With validation and software development becoming a prominent bottleneck in a project, progressive IP providers such as Arasan Chip Systems offer a Total IP Solution to address these demands. In this paper we explore the evolving SoC design model and propose a Total IP Solution approach as the next logical step for IP product companies.
  
  
• My FPGA's not working: Problems with the IP (Feb. 18, 2010)
  In my previous post I waffled on about the challenge of RTL mismatches in an FPGA methodology. This week we'll look at how using third-party IP can also introduce some nasty little issues
  
  
• Re-Configurable Platform for Design, Verification and Implementation of SoCs (Design and Verification without Constraints) (Feb. 11, 2010)
  We propose a new methodology flow which will allow the visual definition of a complex SoC through instantiation of parametric IP such as processors, SDRAM controllers, DMA engines, on-chip buses, peripherals, switch matrices and coherency directories, coprocessors, etc.
  
  
• Module Threading Technique to Improve DRAM Power and Performance (Feb. 01, 2010)
  This paper provides details of all DRAM timing constraints which have heavy impact on memory system performance and introduces module threading technique to overcome these limitations. It also provides detailed theoretical analysis on how module threading can offer finer granularity, higher bandwidth and importantly lower power consumption. It also provides board level analysis where 25% power was saved and a higher performance achieved by adopting module threading technique.
  
  
• Using SerDes in Fourth Generation Wireless Infrastructure (Jan. 26, 2010)
  As the network equipment infrastructure is built up for 4G there will be an demand for high serial data rates between the main control radio equipment and that in distributed base stations. Here is how to meet the high serial data rate by only ugrading the Serdes through the use of a discrete solution
  
  
• A nuts and bolts engineering approach to using open source IP (Jan. 26, 2010)
  Mindtree's Girish Managoli provides some practical advice about preparing the documentation on products based on open source IP, before handing it over to management and the legal department.