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IP / SOC Products Articles

• Low Cost Solution for Microcontroller In-system Power-up Behaviour Evaluation (Dec. 06, 2010)
  This paper discusses about a low cost, portable, reusable platform established to ease the in-system power-up behaviour evaluation of MCU. This flexible platform is able to generate ramp-up signals at different speeds, starting at different initial voltages, which reduce the first silicon evaluation cost and time significantly. The focus would be mainly on 2 aspects; power-up sequence evaluation, and the low cost test setup with thought of reuse.
  
  
• Viewpoint: Need to move beyond the network-on-chip (Jan. 05, 2010)
  With today's design starts using 65nm design rules or smaller, the number of cores in an SoC can exceed 100. Connecting 50 or 100 cores breeds challenges that SoC design teams did not have to previously face.
  
  
• A 66-mW 3.4Gbps Transmitter PHY for HDMI Applications in 2.5V 40-nm CMOS (Jan. 04, 2010)
  This paper presents a low-power Synopsys® DesignWare® High Definition Multimedia Interface Transmitter (HDMI TX) PHY in a 2.5V 40-nm CMOS process. It employs a number of features for IP portability and ultra-low power consumption. The DesignWare HDMI TX IP includes a half-rate serializer, a low-power PLL and clocking scheme in addition to a novel TX architecture. The architecture is portable into both 2.5V and 1.8V process nodes, and makes use of a “supply-less” termination scheme that eliminates the need for a 3.3V supply.
  
  
• Designing Serial ATA IP into your embedded storage device design (Dec. 15, 2009)
  Due to this demand, the SATA interface is increasingly becoming available as third party intellectual property (IP) to help speed development time and lower costs. The quality, completeness and interoperability of this IP become the key considerations to the SoC integrator. This article describes the SATA complete IP solution for both host and device applications.
  
  
• The SoC in 2020: Advances to redefine how we live (Dec. 07, 2009)
  In this fourth installment of TI's 2020 Vision series, Senior Fellow Bill Witowsky (retired) explains why the inherent functionality of future high-performance SoCs will be defined by software in order to facilitate the repurposing required to offset their development costs.
  
  
• PRODUCT HOW-TO: Increase embedded processor efficiency through the use of distributed processing blocks (Nov. 30, 2009)
  How to incorporate distributed multiprocessing in an embedded design using the Cypress PSoC 3/PSoC 5, which incorporate a main 8051 or Cortex M3 core and many Universal Digital Blocks (UDBs) serving as an array of mini-processors.
  
  
• Using IEEE-1588 transparent clocks to improve system time synchronization accuracy (Nov. 30, 2009)
  When deploying IEEE-1588 for system time synchronization in a network design, it is necessary to consider the timing accuracy you require, and how well the slave you want to use performs. Here are the basics on how to achieve this goal.
  
  
• Using OCP and Coherence Extensions to Support System-Level Cache Coherence (Nov. 12, 2009)
  In this paper, the concept of OCP coherence extensions is proposed. Moreover, a possible OCP-based coherence design utilizing the proposed OCP coherence extensions to support system-level cache coherence is also demonstrated.
  
  
• Multi-core, multi-IP reduce development time for infotainment apps (Nov. 09, 2009)
  With its new SH7786, Renesas has expanded its commitment to modular multimedia processors and complete multimedia system solutions for the automotive industry. This evolutionary approach, based on current architectures, ensures low-risk system integration.
  
  
• Incorporating Quality into Reusable Interface IP (Nov. 09, 2009)
  Today’s complex silicon-on-chip (SoC) designs contain multiple instances of silicon intellectual property including CPUs, DSPs, and large numbers of interface IP—SD, SDIO, USB, and MIPI—to store and route video, audio, and data within these designs. On some large SoCs, as much as 85 percent of silicon real estate is made up of third party IP.
  
  
• Graphics processing: When DIY just doesn't make sense (Nov. 05, 2009)
  High-end displays are gaining ground, and designers are urged to develop more advanced graphics processing. To lower the cost of ownership, ARM suggests licensing of an integrated GPU solution that includes software and hardware.
  
  
• Stochastic Computation applied to the design of Error Correcting Decoders (Nov. 05, 2009)
  We describe the application of stochastic computation to a family of error-correcting decoders. We have applied this technology to the Low Density Parity Check (LDPC) codes first described by Gallagher in the 1960s. LDPC is the highest performance error correcting code known to date and is used in IEEE standards including WiFi, WiMAX, DVB-S2, and 10 GbE.
  
  
• Femtocells Gather Momentum - Security Design is Pivotal to Consumer Acceptance (Nov. 02, 2009)
  AT&T customers in Charlotte, North Carolina have the good fortune of being the latest subscribers that are can now able to sign-up for a femtocell which offers consumers reliable, high-bandwidth mobile services at home. A femtocell is a miniaturized version of a cell site that a customer installs at home and connects to a DSL or cable modem. This article offers background on how femtocell networks are constructed, offers a snapshot on standardization and interoperability efforts and then digs in to the important security requirements that are vital to successful deployment of femtocells.
  
  
• A Set of VHDL IPs to Evaluate Performance of Netwoks-on-Chip (Oct. 19, 2009)
  The design of a Network-on-Chip – NoC requires the use of simulation tools to characterize its performance metrics. However, cycle-accurate models are time-costly and the simulation of a large system can consume several hours of computing. The evaluation time can be significantly reduced by running the performance evaluation experiments on a NoC implemented directly on hardware, typically using FPGA.
  
  
• Customizable SoC SPEAr from STMicroelectronics Solving Time to Market Issues (Oct. 05, 2009)
  Some of the most common known issues any equipment manufacturer needs to solve are Time To Market and Time To Volume strong constraints. These issues are also linked with an increased fragmentation of the final products portfolio to be offered, even if often these products are using the same kernel of basic SoC product. SPEAr concept is one of the most suitable versatile but standard SoC for a customer to solve these issues
  
  
• A 24 Processors System on Chip FPGA Design with Network on Chip (Sep. 21, 2009)
  In this paper we present a single FPGA chip implementation of a NOC based shared memory multiprocessor system with 24 processors connected to a main memory composed of 4 DDR2 banks. All the processors and DDR2 memories are connected to a NOC through Open Core Protocol (OCP-IP) interface. The MPSOC have been validated and evaluated through actual execution with matrix multiplication application. A Global Asynchronous Local Synchronous (GALS) design methodology have been adopted throughout the design cycle and exploited for clock trees designs.
  
  
• OTP with a ROM Conversion Option Provides Flexibility and Cost Savings for On-Chip Microcode Storage (Aug. 31, 2009)
  This article covers the flexibility that an OTP with ROM option provides with regard to the product life cycle of high volume products. You will learn how to estimate OTP programming cost and make trade-off analysis to help you decide whether or not a mask ROM conversion makes economical sense.
  
  
• Picking the right MPSoC-based video architecture: Part 4 (Aug. 20, 2009)
  A look at the design of multiprocessor systems-on-chips (MPSoCs) for video applications and how to optimize them for computational power and real-time performance as well as flexibility. Part 4: Application-driven architecture design.
  
  
• Picking the right MPSoC-based video architecture: Part 3 (Aug. 20, 2009)
  A look at the design of multiprocessor systems-on-chips (MPSoCs) for video applications and how to optimize them for computational power and real-time performance as well as flexibility. Part 3: Critical communication bus structures
  
  
• Picking the right MPSoC-based video architecture: Part 2 (Aug. 18, 2009)
  A look at the design of multiprocessor systems-on-chips (MPSoCs) for video applications and how to optimize them for computational power and real-time performance as well as flexibility. Part 2: CPU configurations and interconnections.
  
  
• Picking the right MPSoC-based video architecture: Part 1 (Aug. 18, 2009)
  A look at the design of multiprocessor systems-on-chips (MPSoCs) for video applications and how to optimize them for computational power and real-time performance as well as flexibility. Part 1: Architectural approaches to video processing
  
  
• Embedded Instrumentation Integration Using IEEE Nexus 5001 and 1149.7 (Aug. 13, 2009)
  New capabilities for improving embedded control and visibility for chip level analysis and design for debug logic and interfaces to an IC are needed to enable real time functional control, test, and observation of embedded and otherwise not easily accessible operational features. IEEE 5001, also known as Nexus provides a standard method and architecture for embedded instrument interfaces. New debug and instrumentation capabilities, being introduced by Nexus working groups, include support for IEEE 1149.7, which defines the next generation for (JTAG) Debug and Test Control.
  
  
• A Cost-Optimized Set-Top Box Architecture (Aug. 10, 2009)
  This paper presents a cost-optimized system on chip architecture for cable-based high definition TV set-top box platforms with integrated DOCSIS channel bonding and high speed home networking.
  
  
• IP-based Toolbox for Digital Signal Processing Reuse: Application to Real-time Spike Sorting (Jul. 06, 2009)
  The design flow of digital signal processing has to be improved. In a specific application, we propose a definition of the IP content and the structure of an IP-based toolbox. The case study consists in an clustering algorithm for spike sorting.
  
  
• Modelling OCP Interfaces in SystemC: Standards built on top of OSCI's TLM-2 (Jul. 06, 2009)
  This paper describes the approach adopted by OCP-IP to providing SystemC modelling interfaces for a real memory-mapped bus family. TLM-2.0 has shown itself to be an effective and efficient base technology for all variants of OCP at all levels of abstraction, from cycleaccurate to untimed.
  
  
• SuperSpeed USB 3.0: Ubiquitous Interconnect for Next Generation Consumer Applications (Jun. 22, 2009)
  To address the bandwidth limitations of the USB 2.0 interface, the USB Implementers Forum (USB-IF) released the SuperSpeed USB 3.0 specifications in November 2008. The USB 3.0 specification provides a maximum bandwidth of up to 5Gbps while limiting power consumption. In this white paper we present the features of the USB 3.0 protocol, discuss the new usage models it enables and compare it with some of the existing interface standards popular in the market today.
  
  
• Networks-on-Chip with Reprogrammable Interconnections (Jun. 11, 2009)
  One of ways for enlargement of ASIC based Systems-on-chip field of application is using of internal interconnection system based on reconfigurable Network-on-chip. In this article we suggest some variants of reconfigurable system-on-chip structure based on physical and virtual channels, evaluate their parameters. We suggest mathematical model for relative hardware cost of systems evaluation We compare hardware cost and throughput for these variants of systems.
  
  
• Tailored SoC Building Using Reconfigurable IP Blocks (Jun. 08, 2009)
  Increasing complexity, faster changing standards and shorter time to market ask for composing systems out of standard IP components. An example shows the construction of a System-on-Chip (SoC) based on standard IP components for a Digital Audio Broadcasting consumer application.
  
  
• Can MIPI and MDDI Co-Exist? (Jun. 08, 2009)
  Since MIPI and MDDI standards both target interfaces to cameras and displays on mobile devices, are two separate standards really needed?
  
  
• Adopting An SOC-based Approach to Designing Handheld Medical Devices (May. 28, 2009)
  The rapid growth of the medical devices industry has seen a comparable increase in demand for handheld medical devices, from personal defibulators to continuous glucose monitors. Designing such devices can be a daunting task.