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IP / SOC Products Articles

• H.264 High Profile: Codec for Broadcast & Professional Video Application (May. 20, 2010)
  High definition video content is becoming rampant as more and more countries are now transitioning into digital life. The ways to deliverHigh definition content in a bandwidth limited channel have become challenge in itself. To cater to such highly demanding broadcast & professional video markets, we require a compression / decompression standard that allows no compromise on the quality of the video that has to be broadcasted over a bandwidth constrained networks.
  
  
• A Re-Usable Level 2 Cache Architecture (May. 25, 2009)
  This paper presents the architecture of a high performance level 2 cache capable of use with a large class of embedded RISC cpu cores. The cache has a number of novel features including advanced support for data prefetch, coherency, and performance monitoring. Results are presented showing the performance improvement profile over a large class of applications.
  
  
• New Applications Areas Driving Higher Dynamic Range Converters (May. 18, 2009)
  With the advent of higher broadband speeds in the fixed line and wireless systems, the need for higher performing data converters has become apparent. In this article, we discuss the different standards that are pushing this trend and how single tone testing, in some cases, does not accurately determine the performance in communication systems.
  
  
• USB OTG: The only wired interface portable consumer products need? (Apr. 23, 2009)
  With so many portable product interfaces, UBS On-the-Go is perhaps the best choice in many situations
  
  
• Practical Design and Implementation of a Configurable DDR2 PHY (Apr. 20, 2009)
  To reduce the hassles presented to SoC designers by the DDR2 interface, many problems have been resolved by DDR2 PHY IP development. A DDR2 high speed PHY block is almost always developed as a full custom mixed signal design. There are many good reasons for implementing a full custom design, where every cell and every signal route is fully controlled. Such pre-defined, hard designs offer a way to deal with the tight timing budget of DDR2, which is in the range of a few tens of picoseconds. Another reason is the physical dimensions in which this block must fit. This paper presents through examples of the methods selected while performing physical implementation of the IP.
  
  
• Inside Ceva's high-performance XC core for 4G handsets, infrastructure (Apr. 16, 2009)
  In February CEVA announced a new family of high-performance licensable DSP cores, the CEVA-XC family, targeting 4G cellular applications, including LTE and WiMax -- for both handsets and infrastructure. BDTI went inside and took a look at the company's performance and features claims.
  
  
• Using an interface wrapper module to simplify implementing PCIe on FPGAs (Apr. 09, 2009)
  Stephane Hauradou compares various approaches to implementing PCI Express on FPGAs to the PLDA EZDMA module interface wrapper to provide a simple and robust user interface with PCI Express hard IP.
  
  
• Building advanced Cortex-M3 applications (Apr. 09, 2009)
  The ARM Cortex-M3 architecture provides many improvements compared with its predecessor, the popular ARM7/9, and is designed to be particularly suitable for cost-sensitive embedded applications that require deterministic system behavior. This article describes how developers can best utilize the advanced capabilities of the Cortex-M3 when designing embedded applications.
  
  
• SoC IP Interfaces and Infrastructure -- A Hybrid Approach (Apr. 06, 2009)
  This paper presents three generations of SoC designs beginning with a flat single AHB Bus based interconnect, followed by a multi-tier AHB/APB segmented communication infrastructure and finally our hybrid approach using both the AHB bus for control path operations and point to point BVCI connections through an internal crossbar for data flow. This architecture eliminates many of the dataflow bottlenecks common to SoCs and leaves the device constrained only by processing power and DRAM bandwidth. The power benefits of the architecture are also discussed throughout.
  
  
• Optimization of current-limiting solutions for USB 3.0 (Apr. 06, 2009)
  In addition to transfer speed enhancement in USB 3.0, the requirement for power supply is also increased to meet various peripheral demands. The article introduces the Polymeric Positive Temperature Coefficient (PPTC) device, which is an over-current protection device often used in the industry, and compares it with low-voltage solid-state switch for USB 3.0 applications.
  
  
• M-LVDS for true multipoint interfaces on busses--and more (Mar. 30, 2009)
  Multipoint, low-voltage differential signaling (M-LVDS) is an interface standard similar to LVDS. It provides the benefits of high-speed, low-power, and low-EMI transmission solutions to today's bus applications. M-LVDS is suitable for data, control, synchronization and clock signals.
  
  
• Integrated Power Management, Leakage Control and Process Compensation Technology for Advanced Processes (Mar. 16, 2009)
  This paper describes a unique suite of power management, leakage control and process compensation technology geared towards reducing power while optimizing performance. This integrated solution, including advanced algorithms, innovative circuits, unique devices and structures, software and manufacturing optimization methods, will be discussed. Silicon performance results will be reported.
  
  
• Pipeline vs. Sigma Delta ADC for Communications Applications (Mar. 16, 2009)
  The Analog-to-Digital Converter (ADC) is a key component in digital communications receive channels, and the correct choice of ADC is critical for optimizing system design. In this article, we discuss what design factors drive the selection of the ADC, how to specify the ADC and when to choose between a Pipeline ADC and a Sigma-Delta (Σ/Δ) ADC.
  
  
• Debug and testability features for multi-protocol 10G Serdes (Mar. 09, 2009)
  The paper describes the design-for-test (DFT) features of a 10.3125Gb/s Serdes and other such high datarate IP as XAUI, PCIe, and others. It is shown that extensive testability can be implemented in a high data-rate Serdes. The paper describes the bench-test and characterization features, as well as wafer and production test considerations.
  
  
• The VP8 video codec: High compression + low complexity (Mar. 02, 2009)
  On2 VP8 achieves high compression with a bitstream that is less compute intensive to decode than either its predecessor (VP7) or competing technologies like H.264. Here's how it works.
  
  
• PCI Express Gen 3 Simplified (Feb. 27, 2009)
  In early 2008, the PCI-SIG announced the establishment of a workgroup chartered with the development of the next generation of PCIe " the PCI Express Base Specification 3.0, or PCIe Gen 3. The Gen 3 specification is yet another step forward in enhancing the usefulness of the PCIe protocol by doubling the effective bandwidth and adding protocol enhancements to increase end-system performance.
  
  
• Analysis: BDTI benchmarks the CEVA-TeakLite-III (Feb. 26, 2009)
  BDTI has released BDTI DSP Kernel Benchmarks results for the CEVA-TeakLite-III core from CEVA. The CEVA-TeakLite-III competes with a range of general-purpose DSP and CPU cores from vendors such as VeriSilicon, ARM, and MIPS, and also with application-specific audio solutions, such as Tensilica's 330HiFi audio core and ARC's Sound Subsystems cores.
  
  
• How to pick a RapidIO switch (Feb. 23, 2009)
  Designers have many different options for implementing a RapidIO interconnect. This article outlines the decision factors that designers should consider, organized by project development phases: system design, implementation, system verification, and system evolution. A last section discusses support services, which impact all stages of project development.
  
  
• DDR SDRAM Controller IP Designed for Reuse (Feb. 19, 2009)
  This paper deals with reusability issues in the development of a double data rate (DDR) SDRAM controller module for FPGA-based systems. With our approach, it is possible to generate a highly reconfigurable DDR controller that minimizes the recoding effort for hardware development.
  
  
• Dynamic instruction set load-in method for Java SoC (Feb. 12, 2009)
  There are varieties of embedded systems in the world, it’s a big challenge to optimized the instruction sets of SoCs according to different systems’ working environments. The idea of dynamic instruction set is a good method to achieve the embedded system’s re-configurability. This paper presents a convenient method for a Java processor to work with dynamic instruction set in the form of FPGA or ASIC.
  
  
• Migrating from SPI 4.2 to SPI 5 IP Core - Architectural Changes and Re-usability (Feb. 09, 2009)
  This article discusses the architectural changes and IP re-usability scope for modifying an existing SPI 4.2 Transmitter and Receiver IP Core. SPI 4.2 and SPI 5 have a great deal of functional similarity which makes this IP migration smoother. The paper considers an existing SPI 4.2 IP core and examines the architectural changes and re-usability of the sub-modules. The addition of a few modules, which are a part of SPI 5 protocol, is also highlighted.
  
  
• A Platform for Performance Validation of Memory Controllers (Feb. 02, 2009)
  With growing gap between processor and memory speeds, the memory bandwidth has become performance bottleneck for media applications. The memory controller designs are getting optimized to reduce the latencies added by them. It is necessary to prove the performance of memory controller on prototypes. It has been observed that the performance calculated in simulations is very difficult to achieve on prototype board. This is mainly because of subsystem limitations.
  
  
• SAS--SATA: What You Need to Know for 6 Gb/s and Beyond (Jan. 26, 2009)
  New SAS-2 and SATA Gen-3 system protocols enable 6 Gb/s link speeds between storage units, disk drives, optical and tape drives, and protocol host bus adapters. Here are the challenges to maintaining signal integrity at 6 Gb/s and how improper test setups degrade signals during development and test.
  
  
• Identifying IP cores -- to protect your investment (Jan. 26, 2009)
  In this paper, Semiconductor Insights shows some noble ways of identifying IP cores from any SoC products to protect the interest of IP core providers. Techniques developed by Semiconductor Insights to identify IP core blocks include methods such as circuit extraction using advanced delayering techniques, layout comparisons, automatic recognition and extraction of standard cells and blocks of designs, netlist generation from the extracted circuits, use of circuit library to identify IP blocks, use of structural data mining algorithm for netlist comparison, and device and system level testing to identify IPs involving algorithms and system level protocols.
  
  
• Backplane tutorial: RapidIO, PCIe and Ethernet (Jan. 15, 2009)
  RapidIO, PCIe, and Ethernet each offer unique benefits. We explain how each technology works, and examine its strengths and weaknesses. We also show why RapidIO is often the best choice for embedded systems.
  
  
• Inductorless versus Inductor-Based Integrated Switching Regulators: Bill Of Material, Efficiency, Noise, and Reliability Comparisons (Jan. 12, 2009)
  Inductor-based Switching Regulators (SR) have historically represented the preferred architecture for power supplies. Nowadays, for low-power and highly integrated electronic systems, embedded inductor-based SRs show several limitations that can be overcome by the use of inductorless SR architectures. This paper provides a qualitative and quantitative comparison between both types of SR in terms of implementation cost (Bill of Material, and pin count), and performance (efficiency, noise, and reliability).
  
  
• Providing memory system and compiler support for MPSoc designs: Memory Architectures (Part 1) (Jan. 08, 2009)
  System-on-chip (SoC) architectures are being increasingly employed to solve a diverse spectrum of problems in the embedded and mobile systems domain. The resulting increase in the complexity of applications ported into SoC architectures places a tremendous burden on the computational resources required to deliver the required functionality.
  
  
• Providing memory system and compiler support for MPSoc designs: Customization of memory architectures (Part 2) (Jan. 08, 2009)
  To follow on the review and assessment of various memory architectures in Part 1 in this series, we will now survey some research efforts that address the exploration space involving on-chip memories. A number of distinct memory architectures could be devised to exploit different application-specific memory access patterns efficiently.
  
  
• Providing memory system and compiler support for MPSoc designs: Compiler Support (Part 3) (Jan. 08, 2009)
  An optimizing compiler that targets MPSoC environments should tackle a number of critical issues. From the performance viewpoint, perhaps the two most important memory-related tasks to be performed in an MPSoC environment are optimizing parallelism and locality. Other important issues relate to power/energy consumption and memory space.
  
  
• Differentiate your HD multimedia design by customizing the processor core (Jan. 05, 2009)
  The opportunity for product differentiation and the need for programmability now reside in the video pre- and post-processing blocks that improve upon the picture and color fidelity delivered by the digital HD codecs.