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IP / SOC Products Articles

• A multi-purpose Digital Controlled Potentiometer IP-Core for nano-scale Integration (Nov. 23, 2009)
  This paper presents a highly portable and configurable Digital Controlled Potentiometer (DCP) IP core which comes along with a novel, mainly automated IP integration and characterization process with excellent porting capabilities. The DCP-IP core is optimized to be used as a DAC and an SAR-ADC in a wide specification range.
  
  
• What if the IP you are looking for does not exist? (Oct. 26, 2009)
  Designing a modern SoC is in great part a job of selecting and integrating existing IP cores from third parties. This represents a tremendous acceleration and cost reduction in the design process when compared to maintaining a multidisciplinary design team in house.
  
  
• Enabling Robust and Flexible SOC Designs with AXI to PCIe Bridge Solutions (Sep. 08, 2009)
  A bridge between two standard protocols is an attractive building block for system designers. When designing an application around a standard protocol, a bridge to another protocol enables all of the benefits of that second system with a less-intensive design-process.
  
  
• Placement of different type nodes in a Network-on-chip graph (Aug. 17, 2009)
  In this article we consider effect of different type nodes placement in a network-on-chip to system parameters. We suggest a method of nodes placement that guarantee the potential performance constraints meeting
  
  
• Use open loop analysis to model power converters with multiple feedback paths (Dec. 22, 2008)
  This article capitalizes on work done with loop stability analysis techniques and explores different ways to apply the them to power converters featuring multiple feedback paths
  
  
• A Generalized Waveform Synthesis Mechanism for Software Radio (Dec. 15, 2008)
  This paper describes a generalized method to achieve Direct Waveform Synthesis (DWS) for different modulation formats both binary and multi-level, in order to include this mechanism in the general functioning of a software based IP-core. Moreover a generalized approach for designing and managing of an IP core, which is based on Linear Algebra and specific programming, is derived from the developed algorithm.
  
  
• Video processing pipeline design (Dec. 04, 2008)
  An experienced designer explains the basics of video processing pipelines. He shows how they resemble classic RISC processor pipelines, and the tradeoffs of Tensilica and Silicon Hive solutions.
  
  
• Video encoding with low-cost FPGAs for multi-channel H.264 surveillance (Dec. 01, 2008)
  Building a high-performance, quad-channel H.264 encoder using low-cost, low-power FPGA architecture.
  
  
• Dealing with clock jitter in embedded DDR2/DDR3 DRAM designs: Part 1 (Nov. 27, 2008)
  This series of three articles explores DDR2/DDR3 clock jitter specifications and provides guidance to embedded systems developers on how to apply them and deal with violations when systems encounter them. Part 1 " Defining Clock Jitter
  
  
• Dealing with clock jitter in embedded DDR2/DDR3 DRAM designs: Part 2 (Nov. 27, 2008)
  This series of three articles explores DDR2/DDR3 clock jitter specifications and provides guidance to embedded systems developers on how to apply them and deal with violations when systems encounter problems. Part 2: DDR2/DDR3 Functionality
  
  
• Dealing with clock jitter in embedded DDR2/DDR3 DRAM designs: Part 3 (Nov. 27, 2008)
  This series of three articles explores DDR2/DDR3 clock jitter specifications and provides guidance to embedded systems developers on how to apply them and how to deal with violations when systems encounter them. Part 3: Clock Jitter and Statistics
  
  
• Build low power video SoCs with programmable multi-core video processor IP (Nov. 24, 2008)
  With power consumption comparable to ASICs, this SoC architecture scales to 1080p and beyond.
  
  
• Built-In DMA Engines Unleash Power of PCI Express Switches (Nov. 13, 2008)
  Direct memory access (DMA) technology has been around for more than 20 years. DMA has been used principally to offload memory accesses (reading and/or writing) from the CPU in order to enable the processor to focus on computational tasks and increase the performance of embedded and other system designs.
  
  
• Automotive radio receiver harnesses Software Defined Radio (Nov. 10, 2008)
  Auto-qualified, multi-standard digital radio receiver uses software to implement seven standards; signal-processing blocks are functions that can be shared between different standards.
  
  
• Got OCP? The Role of the OCP in Multicore Designs (Nov. 10, 2008)
  A brief exposition on the role of the open core protocol (OCP) in system-on-chip designs and the impact of the newest Version 3.0 on the design of multiprocessor SoCs.
  
  
• An Integrated, Tunable RF Filter: an Enabler for Reconfigurable Front-Ends (Oct. 27, 2008)
  This paper presents the design and performance of a key RF circuit necessary for the realization of a reconfigurable, integrated RF front-end: a tunable frequency, selectable bandwidth, on-chip, “SAW replacement” filter. The on-die tunable filter presented here has a tunable center frequency up to 1 GHz, a selectable bandwidth up to 40 MHz, and an adjacent channel rejection down to 60 dB.
  
  
• Using signal compression to ease migration to a 4G wireless infrastructure (Oct. 20, 2008)
  By employing signal compression, fiber optic bit rates can be reduced to enable the continued use of low cost fiber optic transceivers.
  
  
• Wireless HDMI with low-latency, lossless H.264 video codec (Oct. 20, 2008)
  Wireless HDMI is impractical for single and multiple 1080p uncompressed video signals, but encoding and decoding traditionally creates A/V sync problems and reduces picture quality. How "Super Low Latency" H.264 codec technology overcomes these problems.
  
  
• Real-time driver drowsiness tracking system (Oct. 16, 2008)
  In which the author describes how an FPGA with a flexible, soft-core embedded processor fuels a real-time driver drowsiness tracking system.
  
  
• Low Power Transport Demultiplexer for ATSC and DVB Broadcast Format (Oct. 09, 2008)
  In this paper, we developed low power transport demultiplexer to support MPEG-2 transport streams for ATSC and DVB digital broadcast standards. Novel window based packet identification (PID) and section filtering is presented to provide a cost effective and flexible solution.
  
  
• Audio ADC buffer design secrets: Interfacing to audio ADC sampling circuits (Oct. 06, 2008)
  Effectively interfacing to A/D converter sampling networks can be a challenging undertaking, but undertsanding the fundamentals can help ensure a successful design.
  
  
• In multicore SOC architectures, buses are a last resort (Oct. 02, 2008)
  The one-processor system model that dominated electronic system design since 1971 is now thoroughly obsolete. Today's SOC designers readily accept the idea of using multiple processors in their complex systems to achieve design goals and use the terms "control plane" and "data plane" to describe how these various on-chip processors are used on the chip.
  
  
• How to transform silicon with dynamic reconfiguration (Oct. 02, 2008)
  A microcontroller capable of reconfiguring its resources needs to provide the integration of an ASIC with the configurability of a FPGA...
  
  
• Using micro-benchmarks to evaluate & compare Networks-on-chip MPSoC designs (Sep. 29, 2008)
  Network-on-Chip (NoC) has been recognized as a promising architecture to accommodate tens, hundreds or even thousand of cores. As a result, a number of NoC architectures have been and are being proposed.
  
  
• A FPGA-Based Solution for Enforcing Dependability and Timeliness in CAN (Sep. 11, 2008)
  This paper identifies a fundamental set of shortcomings of the standard CAN protocol and shows how the problem has been tacked in the implementation of the CANELy architecture, a CAN-based infrastructure able of extremely reliable hard real-time communication.
  
  
• An HDTV SoC Based on a Mixed Circuit-Switched / NoC Interconnect Architecture (STBus/VSTNoC) (Sep. 08, 2008)
  This paper presents the interconnect solution adopted for an HDTV SoC developed in HVD division of STM. The SoC is a one-chip satellite HDTV set-top box IC developed in 65nm technology. The interconnect of this HDTV SoC is the first in STM implementing a mixed archi­tecture based on the circuit-switched interconnect named STBus and the new NoC interconnect named VSTNoC.
  
  
• Reinventing JTAG for SoC debugging (Sep. 08, 2008)
  Want a headstart on implementing a new JTAG debug interface into your design? Here's the lowdown on the soon-to-be IEEE 1149.7 standard.
  
  
• LDPC (Low Density Parity Check) - A Better Coding Scheme for Wireless PHY Layers (Sep. 01, 2008)
  802.16e standard known as the Mobile Wimax standard integrates various coding schemes in the Physical layer specification including the most efficient ones, the LDPC. In this article we will present the physical layer baselines, we will then focus on the error correcting codes to finally detail our implementation.
  
  
• Implementation of the AES algorithm on Deeply Pipelined DSP/RISC Processor (Aug. 20, 2008)
  A more efficient implementation of the Advanced Encryption Standard algorithm on a deeply pipelined RISC/DSP engine reduces overall pipeline stalls during its execution.
  
  
• VLSI Based On Two-Dimensional Reconfigurable Array Of Processor Elements And Theirs Implementation For Numerical Algorithms In Real-Time Systems (Aug. 14, 2008)
  This paper is devoted to the development of one type processor arrays, called MiniTera-2 and to the investigations of realization of some real-time algorithms by means of this array.